公开(公告)号：DE602004005806D1

公开(公告)日：2007-05-24

申请号：DE602004005806

申请日：2004-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALIERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G06F12/06 ,  G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/12

Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.

公开(公告)号：FR2863766A1

公开(公告)日：2005-06-17

申请号：FR0314621

申请日：2003-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G11C8/04 ,  G11C8/12 ,  G06F12/02

Abstract: The memory (MEM) has a comparator, an output buffer, and a central unit preventing execution of read or write command if high order address of extended address is different from that of high order address allocated to the memory. The buffer, the unit and the comparator are arranged to allow the memory to effectuate reading of a plane memory (MA) while preventing data read in the memory (MA) from being applied on serial input/output. An independent claim is also included for a method of manufacturing a plane memory addressable with an extended address.

公开(公告)号：DE602004005806T2

公开(公告)日：2008-01-10

申请号：DE602004005806

申请日：2004-12-08

Applicant: ST MICROELECTRONICS SA

Inventor： ZINK SEBASTIEN ,  CAVALIERI PAOLA ,  LECONTE BRUNO ,  DEVIN JEAN ,  MAUGAIN FRANCOIS

IPC: G06F12/06 ,  G06F3/06 ,  G11C7/10 ,  G11C8/04 ,  G11C8/12

Abstract: The method involves providing a ready/busy pad contact (RBP) in each sequential access memory. A contact management circuit (RBCT) and a central unit are provided in each memory to force the contact to a predetermined electrical potential. Execution of read or write command for integrated plane memory (MA) in each sequential memory is prevented when the contact presents the predetermined potential. An independent claim is also included for a sequential access memory comprising a serial input/output and an integrated plane memory.