公开(公告)号：FR2830124A1

公开(公告)日：2003-03-28

申请号：FR0112377

申请日：2001-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC ,  CORONEL PHILIPPE

IPC: H01L21/8242 ,  H01L27/108

Abstract: Two trenches are dug into an upper insulating layer in such a way that one trench has a width twice that of another trench having a minimum width. The neighboring trenches are separated by a minimum interval and each of the trenches are surrounded with two of the other trenches, respectively. An Independent claim is also included for a dynamic random access memory.

公开(公告)号：FR2828766A1

公开(公告)日：2003-02-21

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2819633A1

公开(公告)日：2002-07-19

申请号：FR0100691

申请日：2001-01-18

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for the integration of a Dynamic Random Access Memory (DRAM), allowing a freedom from the alignment margins inherent in the photoengraving of the upper electrode for the contact passage of the bit line, the retreat of the upper electrode being auto-aligned on the lower electrode, consists of: (a) forming a topographical difference at the spot (A) where the opening for the upper electrode is to be realised; (b) depositing a layer of non-doped polysilicon on the upper electrode; (c) producing an implantation of strongly inclined doping in this layer; (d) selectively engraving the non-doped part of the layer situated in the lower part of the zone (A) presenting the topographical difference; (e) and engraving the remaining part of the polysilicon layer as well as the upper electrode layer situated in the lower part.

公开(公告)号：FR2828764B1

公开(公告)日：2004-01-23

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: This integrated circuit comprises a capacitor ( 23 ) formed above a substrate ( 1 ) inside a first cavity in a dielectric and comprising a first electrode, a second electrode, a thin dielectric layer placed between the two electrodes, and a structure ( 7 ) for connection to the capacitor. The connection structure is formed at the same level as the capacitor in a second cavity narrower than the first cavity, the said second cavity being completely filled by an extension of at least one of the electrodes of the capacitor.

公开(公告)号：FR2832854A1

公开(公告)日：2003-05-30

申请号：FR0115362

申请日：2001-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC

IPC: H01L21/314 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108

Abstract: Dynamic random access memory (DRAM) cells and metal oxide semiconductor (MOS) transistors are manufactured in a semiconductor wafer by forming a capacitor in first (69), second (72), and third (78) insulating layers, enabling balanced distribution of the thicknesses of the insulating layers. Manufacture of DRAM cells in a first region of a semiconductor wafer, each cell including an MOS control transistor (15) and a capacitor and, MOS transistors in a second region of the wafer, the first and second regions are covered with a protection layer (22) and with a first insulating layer, comprises etching at the level of the first region first openings to expose source or drain regions (16) of the control transistors; filling the first openings with a first conductive material (80); re-etching the first conductive material down to part of the depth of the first openings; depositing at the level of the first and second regions a second insulating layer, etching at the level of the first region second openings (74) and at the level of the second region third openings (76) exposing source or drain regions of the transistors, and filling the second and third openings with a second conductive material (82); depositing at the level of the first and second regions a third insulating layer, etching at the level of the first region fourth openings (79) exposing the first conductive material of the first openings, and extending over gates of adjacent control transistors, forming the capacitors at the level of the fourth openings; and etching at the level of the first and second regions fifth openings (84) respectively joining the second and third openings, and filling the fifth openings of the second conductive material to form vias (75, 77).

公开(公告)号：FR2819633B1

公开(公告)日：2003-05-30

申请号：FR0100691

申请日：2001-01-18

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  PIAZZA MARC ,  LEVERD FRANCOIS

IPC: H01L21/8242 ,  H01L27/108

Abstract: The invention relates to a DRAM integration method that does away with the alignment margins inherent to the photoetching step of the upper electrode of the capacitance for inserting the bit line contact. The removal of the upper electrode is self-aligned on the lower electrode of the capacitance. This is accomplished by forming a difference in topography at the point where the opening of the upper electrode is to be made, and depositing a non-doped polysilicon layer on the upper electrode. An implantation of dopants is performed on this layer, and the part of the non-doped layer located in the lower part of the zone showing the difference in topography is selectively etched. The remainder of the polysilicon layer and the part of the upper electrode located in the lower layer are also etched.

公开(公告)号：FR2830124B1

公开(公告)日：2005-03-04

申请号：FR0112377

申请日：2001-09-26

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC ,  CORONEL PHILIPPE

IPC: H01L21/8242 ,  H01L27/108

Abstract: A method for forming in monolithic form a DRAM-type memory, including the steps of forming, on a substrate, parallel strips including a lower insulating layer, a strongly-conductive layer, a single-crystal semiconductor layer, and an upper insulating layer; digging, perpendicularly to the strips, into the upper insulating layer and into a portion of the semiconductor layer, first and second parallel trenches, each first and second trench being shared by neighboring cells; forming, in each first trench, a first conductive line according to the strip width; forming, in each second trench, two second distinct parallel conductive lines, insulated from the peripheral layers; filling the first and second trenches with an insulating material; removing the remaining portions of the upper insulating layer; and depositing a conductive layer.

公开(公告)号：FR2832854B1

公开(公告)日：2004-03-12

申请号：FR0115362

申请日：2001-11-28

Applicant: ST MICROELECTRONICS SA

Inventor： PIAZZA MARC

IPC: H01L21/314 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108

Abstract: Dynamic random access memory (DRAM) cells and metal oxide semiconductor (MOS) transistors are manufactured in a semiconductor wafer by forming a capacitor in first (69), second (72), and third (78) insulating layers, enabling balanced distribution of the thicknesses of the insulating layers. Manufacture of DRAM cells in a first region of a semiconductor wafer, each cell including an MOS control transistor (15) and a capacitor and, MOS transistors in a second region of the wafer, the first and second regions are covered with a protection layer (22) and with a first insulating layer, comprises etching at the level of the first region first openings to expose source or drain regions (16) of the control transistors; filling the first openings with a first conductive material (80); re-etching the first conductive material down to part of the depth of the first openings; depositing at the level of the first and second regions a second insulating layer, etching at the level of the first region second openings (74) and at the level of the second region third openings (76) exposing source or drain regions of the transistors, and filling the second and third openings with a second conductive material (82); depositing at the level of the first and second regions a third insulating layer, etching at the level of the first region fourth openings (79) exposing the first conductive material of the first openings, and extending over gates of adjacent control transistors, forming the capacitors at the level of the fourth openings; and etching at the level of the first and second regions fifth openings (84) respectively joining the second and third openings, and filling the fifth openings of the second conductive material to form vias (75, 77).

公开(公告)号：FR2828766B1

公开(公告)日：2004-01-16

申请号：FR0110866

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/52 ,  H01L27/108 ,  H01L23/498 ,  H01L21/60

Abstract: There is provided an integrated circuit having active components including junctions formed in a monocrystalline substrate doped locally, and at least one passive component situated above the active components. The integrated circuit includes a first insulating layer separating the active components and abase of the passive component, and a metal terminal for electrically connecting the passive component with at least one of the active components. The metal terminal is formed in the thickness of the first insulating layer and has a contact surface that projects from the limits of a junction of the one active component. In a preferred embodiment, the passive component is a capacitor. Also provided is a method of fabricating an integrated circuit that includes MOS transistors and an onboard memory plane of DRAM cells in a matrix.

公开(公告)号：FR2828764A1

公开(公告)日：2003-02-21

申请号：FR0110868

申请日：2001-08-16

Applicant: ST MICROELECTRONICS SA

Inventor： MALLARDEAU CATHERINE ,  MAZOYER PASCALE ,  PIAZZA MARC

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: The invention relates to an integrated circuit comprising: a capacitor (23) which is disposed on top of a substrate (1) inside a first cavity in a dielectric material; a first electrode; a second electrode; a fine dielectric layer which is disposed between the two electrodes; and a structure (7) which connects to the capacitor. Said connecting structure is disposed at the same level as the capacitor in a second cavity which is narrower than the first, said second cavity being entirely filled up by an extension of at least one of the electrodes of the capacitor.