公开(公告)号：FR2783093B1

公开(公告)日：2000-11-24

申请号：FR9811221

申请日：1998-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

IPC: H01L21/02 ,  H01L29/92

Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

公开(公告)号：FR2823598A1

公开(公告)日：2002-10-18

申请号：FR0105015

申请日：2001-04-12

Applicant: ST MICROELECTRONICS SA

Inventor： MENUT OLIVIER ,  JAOUEN HERVE ,  ROBILLIART ETIENNE

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

Abstract: The production of an MOS transistor involves the realization of a MOS transistor of which the gate length, and by consequence essentially the channel length (CHL), is less than the technological limits of photolithography, by forming internal spacers (13) in a cavity of an insulating layer (8) prior to the deposition of the gate material (15). Moreover, the drain and source layers (7) are insulated from the substrate by buried insulating layers (6). Independent claims are also included for the following: (a) a MOS transistor produced as above; and (b) an integrated circuit incorporating at least one MOS transistor thus obtained.

公开(公告)号：FR2783093A1

公开(公告)日：2000-03-10

申请号：FR9811221

申请日：1998-09-04

Applicant: ST MICROELECTRONICS SA

Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

IPC: H01L21/02 ,  H01L29/92

Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.