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    METHOD FOR MAKING A STACK OF CAPACITORS, IN PARTICULAR FOR DIRECT ACCESS DYNAMIC MEMORIES
    1.
    发明申请
    METHOD FOR MAKING A STACK OF CAPACITORS, IN PARTICULAR FOR DIRECT ACCESS DYNAMIC MEMORIES 审中-公开
    用于制造电容器堆叠的方法，特别是直接访问动态记忆

    公开(公告)号：WO0135448A2

    公开(公告)日：2001-05-17

    申请号：PCT/FR0003153

    申请日：2000-11-10

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L

    CPC classification number: H01L27/10852 ,  H01L27/10817 ,  H01L28/60

    Abstract: The invention concerns a method which consists in forming on a substrate (1) coated with a dielectric material layer (3) provided with a window (3a), a stack of successive layers alternately of germanium or SiGe alloy (4, 6, 8) and polycrystalline silicon (5, 7, 9); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material (10) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon (11). The invention is useful for making dynamic random-access memories.

    Abstract translation: 本发明涉及一种方法，该方法包括在涂覆有设置有窗口（3a）的介电材料层（3）的基底（1）上，交替地具有锗或SiGe合金（4,6,8）的叠层， 和多晶硅（5,7,9）; 选择性地部分消除锗或SiGe合金层，形成树状结构; 在树状结构上形成介电材料薄层（10）; 并用多晶硅（11）涂覆树状结构。 本发明对于制作动态随机存取存储器是有用的。

    4.
    发明专利
    未知

    公开(公告)号：FR2838238B1

    公开(公告)日：2005-04-15

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    Semiconductor device with enveloping gate encapsulated in an insulating medium
    6.
    发明专利
    Semiconductor device with enveloping gate encapsulated in an insulating medium 未知

    公开(公告)号：FR2838238A1

    公开(公告)日：2003-10-10

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    Integrated semiconductor memory device and manufacturing method therefor
    9.
    发明专利
    Integrated semiconductor memory device and manufacturing method therefor 审中-公开
    集成半导体存储器件及其制造方法

    公开(公告)号：JP2003060095A

    公开(公告)日：2003-02-28

    申请号：JP2002178046

    申请日：2002-06-19

    Applicant: St Microelectronics Sa ,  エスティマイクロエレクトロニクス エスエー

    Inventor： SKOTNICKI THOMAS ,  VILLARET ALEXANDRE

    IPC: H01L27/10 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L29/42336 ,  H01L29/788

    Abstract: PROBLEM TO BE SOLVED: To provide an integrated semiconductor memory device having hybrid performance. SOLUTION: The integrated semiconductor memory device is provided with an integrated memory structure CH2 provided with a semiconductor layer surrounded by an isolation layer, lying between the source region S and the drain region D of a transistor and inserted between the channel region of the transistor and its control gate. The semiconductor layer included two potential well zones Z1 and Z3 separated by a potential barrier zone Z2 lying beneath the control gate of the transistor. Write means Vg and Vds bias the memory structure so as to confine charge carriers selectively in one or other of the two potential well zones, and read means Vg and Vd bias the memory structure so as to detect, for example by measuring the drain current of the transistor, the presence of charge carriers in one or other of the potential wells.

    Abstract translation: 要解决的问题：提供具有混合性能的集成半导体存储器件。 解决方案：集成半导体存储器件设置有集成存储器结构CH2，其设置有由隔离层围绕的半导体层，该隔离层位于晶体管的源极区域S和漏极区域D之间，并且插入在晶体管的沟道区域和晶体管的沟道区域之间 其控制门。 半导体层包括由位于晶体管的控制栅极下方的势垒区Z2分开的两个势阱区Z1和Z3。 写装置Vg和Vds偏置存储器结构，以便将电荷载流子选择性地限制在两个势阱区域中的一个或另一个中，并且读装置Vg和Vd偏置存储器结构，以便例如通过测量漏极电流 晶体管，在一个或另一个势阱中存在电荷载体。

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