中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.027 seconds)

    3.
    发明专利
    未知

    公开(公告)号：FR2838238B1

    公开(公告)日：2005-04-15

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    Semiconductor device with enveloping gate encapsulated in an insulating medium
    5.
    发明专利
    Semiconductor device with enveloping gate encapsulated in an insulating medium 未知

    公开(公告)号：FR2838238A1

    公开(公告)日：2003-10-10

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    SUBSTRAT HYBRIDE A ISOLATION AMELIOREE ET PROCEDE DE REALISATION SIMPLIFIE D'UN SUBSTRAT HYBRIDE
    9.
    发明专利
    SUBSTRAT HYBRIDE A ISOLATION AMELIOREE ET PROCEDE DE REALISATION SIMPLIFIE D'UN SUBSTRAT HYBRIDE 未知

    公开(公告)号：FR2954584A1

    公开(公告)日：2011-06-24

    申请号：FR0906233

    申请日：2009-12-22

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： FENOUILLET BERANGER CLAIRE ,  DENORME STEPHANE ,  CORONEL PHILIPPE

    IPC: H01L21/762 ,  H01L23/12

    Abstract: Un substrat hybride comporte des première (1) et seconde (3) zones actives en matériaux semi-conducteur décalées latéralement et séparées par une zone d'isolation (5). Les surfaces principales de la zone d'isolation (5) et de la première zone active (1) forment un plan. Le substrat hybride est obtenu à partir d'un substrat souche comportant successivement des couches en premier (2) et second (4) matériaux semi-conducteurs séparées par une couche d'isolation (6). Un unique masque de gravure est utilisé pour structurer la zone d'isolation (5), la première zone active (1) et la seconde zone active (3). La surface principale de la première zone active (1) est libérée formant ainsi des zones vides dans le substrat souche. Le masque de gravure est éliminé au dessus de la première zone active (1). Un premier matériau d'isolation est déposé, aplani et gravé jusqu'à libérer la surface principale de la première zone active (1).

Patent Agency Ranking