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    2.
    发明专利
    未知

    公开(公告)号：DE602006010452D1

    公开(公告)日：2009-12-31

    申请号：DE602006010452

    申请日：2006-02-07

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： TELANDRO VINCENT ,  MALHERBE ALEXANDRE ,  KUSSENER EDITH

    IPC: G06K19/073

    Abstract: The circuit has a linear regulator (4`) for supplying a DC supply voltage (Vdd) to an internal load (29) from an external voltage (Vps). Chopper type capacitive clipping supply circuits (5), with switched capacitances, are in parallel with the activated linear regulator. The circuits supply current at the same time as the linear regulator, during an operation phase (D) of the integrated circuit which corresponds to a phase in which a calculating processor which contains the internal load is active.. An independent claim is also included for a method for scrambling the current signature of a load including an integrated circuit.

    3.
    发明专利
    未知

    公开(公告)号：FR2881851B1

    公开(公告)日：2007-04-13

    申请号：FR0550366

    申请日：2005-02-08

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： MALHERBE ALEXANDRE ,  KUSSENER EDITH ,  TALENDRO VINCENT

    IPC: G06F1/00 ,  G06K19/073

    Abstract: The circuit has a linear regulator (4`) for supplying a DC supply voltage (Vdd) to an internal load (29) from an external voltage (Vps). Chopper type capacitive clipping supply circuits (5), with switched capacitances, are in parallel with the activated linear regulator. The circuits supply current at the same time as the linear regulator, during an operation phase (D) of the integrated circuit which corresponds to a phase in which a calculating processor which contains the internal load is active.. An independent claim is also included for a method for scrambling the current signature of a load including an integrated circuit.

    ALIMENTATION SECURISEE D'UN CIRCUIT INTEGRE
    7.
    发明专利
    ALIMENTATION SECURISEE D'UN CIRCUIT INTEGRE 未知

    公开(公告)号：FR2881851A1

    公开(公告)日：2006-08-11

    申请号：FR0550366

    申请日：2005-02-08

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： MALHERBE ALEXANDRE ,  KUSSENER EDITH ,  TALENDRO VINCENT

    IPC: G06F1/00 ,  G06K19/073

    Abstract: L'invention concerne un procédé et un circuit de brouillage de la signature en courant d'une charge (29) comportant au moins un circuit intégré exécutant des traitements numériques, consistant à alimenter au moins le circuit intégré à partir d'une tension d'alimentation (Vps) externe au circuit en combinant un courant (Ipsdc) fourni par un premier régulateur linéaire (4') avec un courant (Ipsac) fourni par au moins un circuit d'alimentation à découpage capacitif (5) à une ou plusieurs capacités commutées.

    8.
    发明专利
    未知

    公开(公告)号：FR2886426B1

    公开(公告)日：2007-08-31

    申请号：FR0551377

    申请日：2005-05-25

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： KUSSENER EDITH ,  TELANDRO VINCENT ,  CHAILLAN FABIEN

    IPC: G06F7/58

    Abstract: The generator has an oscillator circuit (2) whose polarization is controlled by an analog polarization circuit (5). The circuit (5) is controlled by a continuous time and amplitude variation signal produced by a sample-and-hold circuit (63). An output signal of an analog signal generator (64) is sampled with pseudorandom instant by the circuit (63) at each time when an output signal of a pseudorandom signal source (61) crosses a threshold fixed by a detector (62) : An independent claim is also included for a method of controlling a pseudorandom number generator.

    9.
    发明专利
    未知

    公开(公告)号：FR2814253B1

    公开(公告)日：2002-11-15

    申请号：FR0011800

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SA

    Inventor： KUSSENER EDITH

    IPC: G05F3/30 ,  G05F3/20

    Abstract: A regulated voltage generator provides different regulated voltages to an integrated circuit. The regulated voltage generator includes a bandgap reference circuit and at least one gain stage connected to an output thereof. The output voltage of the bandgap reference circuit varies as a function of temperature to compensate for variations in the gain stage made up of first and second transistors. A regulated voltage output by the regulated voltage generator is independent of temperature and of the supply voltage. The value of the regulated voltage is adjusted via a load resistor and via the first and second transistors along with an output transistor of the bandgap reference circuit.

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