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38 records (took 0.111 seconds)

    2.
    发明专利
    未知

    公开(公告)号：DE602006010452D1

    公开(公告)日：2009-12-31

    申请号：DE602006010452

    申请日：2006-02-07

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： TELANDRO VINCENT ,  MALHERBE ALEXANDRE ,  KUSSENER EDITH

    IPC: G06K19/073

    Abstract: The circuit has a linear regulator (4`) for supplying a DC supply voltage (Vdd) to an internal load (29) from an external voltage (Vps). Chopper type capacitive clipping supply circuits (5), with switched capacitances, are in parallel with the activated linear regulator. The circuits supply current at the same time as the linear regulator, during an operation phase (D) of the integrated circuit which corresponds to a phase in which a calculating processor which contains the internal load is active.. An independent claim is also included for a method for scrambling the current signature of a load including an integrated circuit.

    3.
    发明专利
    未知

    公开(公告)号：FR2881851B1

    公开(公告)日：2007-04-13

    申请号：FR0550366

    申请日：2005-02-08

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： MALHERBE ALEXANDRE ,  KUSSENER EDITH ,  TALENDRO VINCENT

    IPC: G06F1/00 ,  G06K19/073

    Abstract: The circuit has a linear regulator (4`) for supplying a DC supply voltage (Vdd) to an internal load (29) from an external voltage (Vps). Chopper type capacitive clipping supply circuits (5), with switched capacitances, are in parallel with the activated linear regulator. The circuits supply current at the same time as the linear regulator, during an operation phase (D) of the integrated circuit which corresponds to a phase in which a calculating processor which contains the internal load is active.. An independent claim is also included for a method for scrambling the current signature of a load including an integrated circuit.

    ALIMENTATION SECURISEE D'UN CIRCUIT INTEGRE
    6.
    发明专利
    ALIMENTATION SECURISEE D'UN CIRCUIT INTEGRE 未知

    公开(公告)号：FR2881851A1

    公开(公告)日：2006-08-11

    申请号：FR0550366

    申请日：2005-02-08

    Applicant: ST MICROELECTRONICS SA ,  UNIV D AIX MARSEILLE I

    Inventor： MALHERBE ALEXANDRE ,  KUSSENER EDITH ,  TALENDRO VINCENT

    IPC: G06F1/00 ,  G06K19/073

    Abstract: L'invention concerne un procédé et un circuit de brouillage de la signature en courant d'une charge (29) comportant au moins un circuit intégré exécutant des traitements numériques, consistant à alimenter au moins le circuit intégré à partir d'une tension d'alimentation (Vps) externe au circuit en combinant un courant (Ipsdc) fourni par un premier régulateur linéaire (4') avec un courant (Ipsac) fourni par au moins un circuit d'alimentation à découpage capacitif (5) à une ou plusieurs capacités commutées.

    Device for the regeneration of a clock signal
    8.
    发明授权
    Device for the regeneration of a clock signal 有权
    用于再生时钟信号的装置

    公开(公告)号：US6362671B2

    公开(公告)日：2002-03-26

    申请号：US77136401

    申请日：2001-01-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： MALHERBE ALEXANDRE ,  MARINET FABRICE ,  POMET ALAIN

    IPC: G06F13/42 ,  G06K19/07 ,  H03K5/01

    CPC classification number: G06K19/07 ,  G06F13/426

    Abstract: A device for the regeneration of a clock signal from an external serial bus includes a ring oscillator and counter. The ring oscillator provides n phases of a clock signal. Of these n phases, one phase is used as a reference and is applied to the counter. It is thus possible to count the number of entire reference clock signal periods between a first pulse and a second pulse received from the bus. In reading the state of the phases in the oscillator upon reception of the second pulse, a determination is made for a current phase corresponding to the phase delay between the reference clock signal and the second pulse of the bus. By using a regeneration device that also includes a ring oscillator and a counter, it is possible to regenerate the clock signal of the bus with high precision.

    Abstract translation: 用于从外部串行总线再生时钟信号的装置包括环形振荡器和计数器。 环形振荡器提供时钟信号的n个相位。 在这n个阶段中，使用一个相作为参考，并将其应用于计数器。 因此，可以对从总线接收的第一脉冲和第二脉冲之间的整个参考时钟信号周期的数量进行计数。 在接收到第二脉冲时读取振荡器中的相位状态，确定与基准时钟信号和总线的第二脉冲之间的相位延迟相对应的电流相位。 通过使用还包括环形振荡器和计数器的再生装置，可以高精度地重新生成总线的时钟信号。

    10.
    发明专利
    未知

    公开(公告)号：FR2846791A1

    公开(公告)日：2004-05-07

    申请号：FR0213690

    申请日：2002-10-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： BARDOUILLET MICHEL ,  MALHERBE ALEXANDRE

    IPC: H01L21/02 ,  H01L27/08 ,  H01L23/64 ,  H01L21/326 ,  H01C7/13

    Abstract: A resistive element controllable to irreversibly decrease its value, including several polysilicon resistors connected in series between two input/output terminals of the resistive lemen; and an assembly of switches, connected to turn the series connection into a parallel association of said resistors between two programming terminals intended to receive a supply voltage.

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