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    3.
    发明专利
    未知

    公开(公告)号：DE60303187D1

    公开(公告)日：2006-04-06

    申请号：DE60303187

    申请日：2003-03-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ALBASINI GUIDO GABRIELE ,  TEMPORITI MILANI ENRICO

    IPC: H03L7/197

    Abstract: A fractional-type phase-locked loop circuit (100), for synthesising an output signal (So) multiplying a frequency of a reference signal (Sr) by a selected fractional conversion factor, includes a frequency divider (105) for generating a feedback signal (Sb) dividing the frequency of the output signal by a frequency division factor selectable among at least two different integer-value division factors, and frequency divider control means (110;510) for causing the frequency division factor to vary between the at least two integer-value division factors in a pre-defined number of cycles, thereby an average frequency division factor over said pre-defined number of cycles has a fractional value. Means (125a;125b;125c) are provided for compensating a phase error introduced by the frequency divider on the basis of a value indicative of the phase error (ACC;APE) obtained from said frequency divider control means. The phase-error compensation means includes rounding means (170a;170b), receiving an input binary code (ACC;APE) with a first number of binary digits, indicative of the phase error value, and providing an output binary code (ACR;APER), with a second number of binary digits lower than the first number of digits, defining a rounded phase error value.

    4.
    发明专利
    未知

    公开(公告)号：DE60302543D1

    公开(公告)日：2006-01-05

    申请号：DE60302543

    申请日：2003-03-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ALBASINI GUIDO GABRIELE ,  TEMPORITI MILANI ENRICO

    IPC: H03L7/089 ,  H03L7/197 ,  H03M1/74 ,  H04L25/34

    Abstract: A fractional-type phase-locked loop circuit (100) is proposed for synthesising an output signal multiplying a frequency of a reference signal by a fractional conversion factor, the circuit including means (110) for generating a modulation value, means (105) for generating a feedback signal dividing the frequency of the output signal by a dividing ratio, the dividing ratio being modulated according to the modulation value for providing the conversion factor on the average, means (115,120) for generating a control signal indicative of a phase difference between the reference signal and the feedback signal, means (135,140) for controlling the frequency of the output signal according to the control signal, and means (125,130) for compensating a phase error caused by the modulation of the dividing ratio; in the circuit of the invention, the means for compensating includes means (305-310) for calculating an incremental value, indicative of an incremental phase error, according to the conversion factor and the modulation value, means (315-320) for calculating a correction value accumulating the incremental value, and means (130) for conditioning the control signal according to the correction value.

    6.
    发明专利
    未知

    公开(公告)号：DE60302867D1

    公开(公告)日：2006-01-26

    申请号：DE60302867

    申请日：2003-03-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： ALBASINI GUIDO GABRIELE ,  TEMPORITI MILANI ENRICO ,  RICOTTI GIULIO ,  FRATTINI GIOVANNI

    IPC: H03L7/08 ,  H03L7/089 ,  H03L7/093 ,  H03L7/197

    Abstract: A phase-locked loop circuit (100) is proposed for providing an output signal having a frequency depending on the frequency of a reference signal, the circuit including means (105-110) for deriving a feedback signal from the output signal, means (115-120) for providing a control signal indicative of a phase difference between the reference signal and the feedback signal, means (140-145) for controlling the frequency of the output signal according to the control signal, and means (125-135) for conditioning the control signal through at least one conditioning signal; in the circuit of the invention, the means for conditioning includes means (135) for accumulating an energy provided by the control signal and the at least one conditioning signal during a first phase and for transferring the accumulated energy to the means for controlling the frequency of the output signal during a second phase.

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