公开(公告)号：JP2000174626A

公开(公告)日：2000-06-23

申请号：JP33007299

申请日：1999-11-19

Applicant: ST MICROELECTRONICS SRL

Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12

Abstract: PROBLEM TO BE SOLVED: To provide a flash analog/digital converter capable of outputting a temperature measurement digital code. SOLUTION: This flash analog/digital converter is provided with a bank composed of comparators (COMPi) provided with differential output for generating a temperature measurement code and 3-input (A, B and C) logical NOR gates (NORj) and is provided with a passive interface respectively composed of the plural pieces of voltage dividers (Ra-Rb) connected between the non- inverted output (out-p) of the respective comparators (COMPi) and the inverted output (out-n) of the comparators (COMPi+1) of the higher order of the bank. The corresponding logical NOR gate (NORj) of the bank is provided with first input (A) connected to the inverted output (out-n) of the respective comparators (COMPi-1), second input (B) connected to the non-inverted output (out-p) of the comparators (COMPi) of the higher order and third input (C) connected to the intermediate tap of the voltage dividers (Ra-Rb).

公开(公告)号：JP2000013185A

公开(公告)日：2000-01-14

申请号：JP13422999

申请日：1999-05-14

Applicant: ST MICROELECTRONICS SRL

Inventor： DE MICHELI MARCO ,  PORTALURI SALVATORE ,  BOLLATI GIACOMINO ,  BRUCCOLERI MELCHIORRE

IPC: G05F3/26 ,  H03F3/30 ,  H03H11/04

Abstract: PROBLEM TO BE SOLVED: To shorten transconductance stable time after a request for changing the interruption frequency of a filter by installing a feedback loop between the output/input of a transconductor connected to DAC so that reference current is set and making reference current which is set by DAC into a mirror image. SOLUTION: In a master section circuit, output current IR from DAC 7, which is set by reference current generated by a current source 8 and digital word FC-WORD, is made into a mirror image by a PMOS transistor 20 which is diode-connected. Current which is made into the mirror image is sent later from a PMOS transistor 21 to an NMOS transistor 22. It is made into the mirror image in an NMOS transistor 23. The drain terminal of the transistor 23 is connected to a node 6 and a capacitor 5 is connected to the node 6. Thus, the transistor 22 sets the current of the transistor 23.

公开(公告)号：JP2000195169A

公开(公告)日：2000-07-14

申请号：JP35109399

申请日：1999-12-10

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  MALFA MAURIZIO ,  BOLLATI GIACOMINO

IPC: G11B5/09 ,  G11B5/012 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for pre-compensating interference between marks in a large capacity storage device. SOLUTION: This device supplys a digital data stream (I) and a clock signal (Ck) to be stored in a 1st circuit and also makes the 1st circuit(CC1) output a pair of digital streams (N, R). Further, the digital streams (N, R) and the clock signal (Ck) are supplied to a 2nd circuit (DC1), and the 2nd circuit outputs a digital data stream (O) directed to a write head. In such a case, by sampling the two digital streams (N, R) by a pair of flip-flops (FN2, FR2) and also re- coupling the signals outputted from the pair of flip-flops (FN1, FR2) with a digital data stream (O) via a logical XOR gate (X1), the device delays a transition immediately following a preceding transition by a predetermined time interval (Δwp).

公开(公告)号：JP2000166237A

公开(公告)日：2000-06-16

申请号：JP11667499

申请日：1999-04-23

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  OTTINI DANIELE ,  DEMICHELI MARCO ,  BOLLATI GIACOMINO

IPC: H02M7/02 ,  G01R19/22 ,  H02M7/12 ,  H03F3/45

Abstract: PROBLEM TO BE SOLVED: To reduce higher harmonics and dynamic distortion by receiving a differential logical synchronizing signal at the input terminal of a timing circuit, and supplying the first differential timing signal to a track-and-hold stage and the second differential timing signal to a flip flop, respectively. SOLUTION: Differential logical synchronizing signals Clk+, Clk- are received at the input terminal of a timing circuit, and the first differential timing signals TClK+, TClK- are outputted to a differential track-and-hold stage TandH at an output terminal. The second differential timing signals DClK+, DClK- are outputted to a flip flop LATCH-ECL at the output terminal of the timing circuit. The differential track-and-hold stage TandH tracks differential analog input signals IN+, IN- during the tracking phase of the first differential timing signals TClK+, TClK-. The differential flip flop LaATCH-ECL outputs the third differential logical control signals S+, S-.

公开(公告)号：WO2007096919A8

公开(公告)日：2007-12-13

申请号：PCT/IT2006000114

申请日：2006-02-27

Applicant: ST MICROELECTRONICS SRL ,  BOLLATI GIACOMINO ,  BOSI ALESSANDRO ,  CESURA GIOVANNI ANTONIO

Inventor： BOLLATI GIACOMINO ,  BOSI ALESSANDRO ,  CESURA GIOVANNI ANTONIO

IPC: G11B9/02

CPC classification number: B82Y10/00 ,  G11B5/86 ,  G11B9/02 ,  G11B9/1418 ,  G11B11/002

Abstract: A transducer (3) for a storage medium (5) is provided with a supporting element (9) positione

Abstract translation: 用于存储介质（5）的传感器（3）设置有支撑元件（9）

公开(公告)号：DE69825060D1

公开(公告)日：2004-08-19

申请号：DE69825060

申请日：1998-12-17

Applicant: ST MICROELECTRONICS SRL

Inventor： BOLLATI GIACOMINO ,  ALINI ROBERTO ,  OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE

IPC: H03H11/04

Abstract: A low pass filter with programmable equalization comprising at least a biquadratic cell (BIQUAD) and a converter of the input voltage (Vin) in a current (iz), proportional to the derivative of the input voltage, that is injected on a node of the biquadratic cell (BIQUAD) in order to introduce two real and opposed zeroes in the transfer function of the filter, is composed of two structurally similar circuits, functionally connected in cascade, each circuit being composed of a biquadratic cell and an input stage having two outputs injecting through a first current output (A) said current (iz) on an input capacitor (C1) of the respective biquadratic cell, by a direct coupling in a first of said two circuits and in an inverted manner in the second of said two circuits; a second voltage output (B) being coupled to an input of the respective biquadratic cell.

公开(公告)号：ITVA990020D0

公开(公告)日：1999-07-16

申请号：ITVA990020

申请日：1999-07-16

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMICHELI MARCO ,  BOLLATI GIACOMINO ,  DEMICHELI DAVIDE ,  MARCHESE STEFANO

IPC: G11B20/10

Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.

公开(公告)号：DE69833932D1

公开(公告)日：2006-05-11

申请号：DE69833932

申请日：1998-04-23

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  OTTINI DANIELE ,  DEMICHELI MARCO ,  BOLLATI GIACOMINO

IPC: G01R19/04 ,  H02M7/02 ,  G01R19/22 ,  H02M7/12 ,  H03F3/45

Abstract: A full-wave rectifier for monitoring the amplitude of a differential analog signal (IN+, IN-) is composed of a differential Track&Hold stage (T&H) controlled by a first differential logic timing signal (TClk+, TClk-), tracking the differential analog input signal (IN+, IN-) during a tracking phase that corresponds to a high logic stage of the first differential timing signal (TClk+, TClk-), producing a differential output signal that is a replica of the input signal and storing it during a successive storing phase that corresponds to a low logic state of the first differential timing signal (TClk+, TClk-); a first differential output amplifier ( @ ) having inputs coupled to the output of the Track&Hold stage (T&H); a differential bistable circuit (LATCH-ECL), controlled by a second differential logic timing signal (DClk+, DClk-), having inputs coupled to the differential outputs of the first amplifier ( @ ) and producing a third differential logic control signal (S+, S-); a second multiplexed amplifier (Analog-Amp @ ), controlled by the third differential control signal (S+, S-), having inputs coupled to the output of the Track&Hold stage (T&H) and outputting a differential analog signal (OUT+, OUT-) of amplitude function of the amplitude of the differential input signal (IN+, IN-); a timing circuit (T @ C @ ) receiving at an input a differential logic synchronism signal (Clk+, Clk-) and generating the first differential timing signal (TClk+, TClk-) of said Track&Hold stage (T&H) and the second differential timing signal (DClk+, DClk-) of said bistable circuit (LATCH-ECL).

公开(公告)号：DE69825250D1

公开(公告)日：2004-09-02

申请号：DE69825250

申请日：1998-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： DE MICHELI MARCO ,  PORTALURI SALVATORE ,  BOLLATI GIACOMINO ,  BRUCCOLERI MELCHIORRE

IPC: G05F3/26 ,  H03F3/30 ,  H03H11/04

Abstract: A transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor (4) across which a constant voltage is input; the transconductor is connected to a DAC (7) to set a reference current (IR); a feedback loop (9, 10, 23, 11) is provided between the output of the transconductor (4) and its input; the particularity of the circuit is the fact that it further comprises means (20, 22, 24) for mirroring the reference current (IR) set by the DAC (7) which are suitable to mirror the current both to the feedback loop and to at least one cell of a filter which is cascade-connected.

公开(公告)号：DE69803856D1

公开(公告)日：2002-03-21

申请号：DE69803856

申请日：1998-11-27

Applicant: ST MICROELECTRONICS SRL

Inventor： OTTINI DANIELE ,  BRUCCOLERI MELCHIORRE ,  BOLLATI GIACOMINO ,  DEMICHELI MARCO

IPC: H03M1/36 ,  H03M1/08 ,  H03M1/12 ,  H03M7/16

Abstract: A flash analog-to-digital converter comprising a bank of comparators (COMPi) with a differential output, generating a thermometric code and a bank of three-input (A,B,C) logic NOR gates (NORj) for correcting errors in said thermometric code, has enhanced immunity to noise and reduced imprecisions, especially at high conversion rates upon occurence of metastability within the comparators, by providing for a passive interface constituted by a plurality of voltage dividers (Ra-Rb), each connected between the noninverted output (out_p) of a respective comparator (COMPi) and the inverted output (out_n) of the comparator of higher order (COMPi+1) of said bank; a corresponding logic NOR gate (NORj) of said bank having a first input (A) coupled to the inverted output (out_n) of said respective comparator (COMPi-1), a second input (B) coupled to the noninverted output (out_p) of said comparator (COMPi) of higher order and a third input (C) coupled to an intermediate tap of said voltage divider (Ra-Rb).