3.
    发明专利
    未知

    公开(公告)号:DE602004009150D1

    公开(公告)日:2007-11-08

    申请号:DE602004009150

    申请日:2004-02-18

    Abstract: A dither matrix is applied to a high-resolution image to compare the value of each of the pixels that compose it with a threshold value of the matrix and to obtain an output value of the matrix (Dither matrix value) from each comparison. To each pixel value (in_value_r) of the image there is applied the algorithm represented by the schematic layout of Figure 7 to obtain the pixel values (Out_r) of a low-resolution image. C1-C5 and n1-n10 are parameters that may be selected by means of predetermined criteria based on comparisons of the low-resolution image, obtained by means of the operations described above, with an equivalent low-resolution image obtained by means of a sample method.

    4.
    发明专利
    未知

    公开(公告)号:DE60315407D1

    公开(公告)日:2007-09-20

    申请号:DE60315407

    申请日:2003-02-06

    Abstract: A method for texture compressing images having a plurality of color components (R, G, B), includes the step of decomposing the images in sub-blocks each including only one color component. At least one first predictor is defined for each said sub-block and a respective set of prediction differences is computed for each sub-block. Then the prediction differences for each sub block are sorted, and a look-up prediction differences palette is set up by defining therefrom a look-up prediction error palette. A code is associated with each column of the error palette.

    5.
    发明专利
    未知

    公开(公告)号:DE60216268D1

    公开(公告)日:2007-01-04

    申请号:DE60216268

    申请日:2002-08-08

    Abstract: A built-in self-test (BIST) circuit adapted to be embedded in an integrated circuit (101) for testing the integrated circuit, including in particular a collection of addressable elements, for example a semiconductor memory. The BIST circuit comprises a general-purpose data processor (105) programmable for executing a test program for testing the integrated circuit. The BIST circuit comprises an accelerator circuit (113) cooperating with the general-purpose data processor for autonomously conducting operations on the integrated circuit according to the test program. The accelerator circuit comprises configuration means (201,203,233,301,303,501) adapted to be loaded with configuration parameters for adapting the accelerator circuit to the specific type of integrated circuit and the specific type of test program. (FIG. 1)

    8.
    发明专利
    未知

    公开(公告)号:DE60325954D1

    公开(公告)日:2009-03-12

    申请号:DE60325954

    申请日:2003-07-07

    Abstract: A graphic system comprising a pipelined tridimensional graphic engine for generating image frames for a display inlcudes a graphic engine (110;210) comprising at least one geometric processing elaboration stages (111, 112), performing motion motion extraction. The engine also includes a rendering stage (113) generating full image frames (KF) at a first frame rate (F2) to be displayed at a second frame rate (F1), higher than the first frame rate (F2). The pipelined graphic engine further comprises a motion encoder (214) receiving motion vector information (MB) and suitable for coding the motion information e.g. with a variable length code, while generating a signal (R4) representative of interpolated frames (IF). The motion encoder (214) exploits the motion information (MB) as generated by the geometric elaboration stages (211, 212). A motion compensation stage (237) is provided fed with the signal representative of interpolated frames (IF) and full image frames for generating said the interpolated frames (IF). A preferred application is in graphic engines intended to operate in association with smart displays through a wireless connection, i.e. in mobile phones.

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