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    VOLTAGE REGULATOR
    2.
    发明专利
    VOLTAGE REGULATOR 失效

    公开(公告)号：JPH07220490A

    公开(公告)日：1995-08-18

    申请号：JP32565394

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASAGRANDE GIULIO ,  CAMERLENGHI EMILIO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To make the voltage drop of a circuit element the function of the actual length of a memory cell by incorporating the circuit element to a voltage adjuster. CONSTITUTION: The voltage adjuster 3 is provided with a gain stage, which is provided with an input terminal connected to the voltage divider 6 of a programming voltage VPP and an output terminal U connected with the programming line 5 of at least one memory cell 2 and supplied with programming voltage VPP. In addition at least one circuit element 4 compensating the fluctuation of a percentage by a programming line voltage for the length of the memory cell 2 is provided.

    VOLTAGE REGULATOR
    3.
    发明专利
    VOLTAGE REGULATOR 失效

    公开(公告)号：JPH07220491A

    公开(公告)日：1995-08-18

    申请号：JP32565494

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMERLENGHI EMILIO ,  CASAGRANDE GIULIO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: PURPOSE: To make a programming line voltage the function of the actual length of a memory cell by incorporating a circuit element to a voltage adjuster. CONSTITUTION: The voltage adjuster 3 is provided with a gain stage, which is provided with an input terminal connected to the voltage divider 6 of a programming voltage VPP and an output terminal U connected with he programming line 5 of at least one memory cell 2 and supplied with programming voltage VPP. In addition at least one circuit element capable of suiting a programming line voltage to the length of the memory cell 2 is provided. The circuit element is the voltage divider 6 of the programming voltage VPP and is provided with variable resistance values R1 to R3.

    5.
    发明专利
    未知

    公开(公告)号：DE60217120T2

    公开(公告)日：2007-10-25

    申请号：DE60217120

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  BEZ ROBERTO

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: The cell array includes number of N-type base regions (12) which are provided overlying a P-type common collector region (11) in a body (10). P-type emitter regions (14) and N-type base contact regions (15) are formed in the base regions such that the base contact regions have a doping level higher than the doping level of the base regions and each base regions is shared by at least two bipolar transistors (20). An independent claim is also included for a cell array manufacturing process.

    6.
    发明专利
    未知

    公开(公告)号：DE69325278T2

    公开(公告)日：1999-11-11

    申请号：DE69325278

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASAGRANDE GIULIO ,  CAMERLENGHI EMILIO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

    7.
    发明专利
    未知

    公开(公告)号：DE69325278D1

    公开(公告)日：1999-07-15

    申请号：DE69325278

    申请日：1993-12-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CASAGRANDE GIULIO ,  CAMERLENGHI EMILIO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30

    Abstract: A voltage regulator for electrically programmable non-volatile semiconductor memory devices of the type comprising a gain stage (3), supplied by a programming voltage (Vpp) and having an input terminal connected to a divider (6) of said programming voltage (Vpp) and an output terminal (U) connected to a programming line (5) of at least one memory cell (2) comprises at least one circuit element (4) capable of adapting the line programming voltage (5) to the length (L) of the memory cell (2). This solution makes it possible to have on the bit line of the memory device a drain voltage varying according to the actual length of the memory cell.

    9.
    发明专利
    未知

    公开(公告)号：DE60217120D1

    公开(公告)日：2007-02-08

    申请号：DE60217120

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  BEZ ROBERTO

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: The cell array includes number of N-type base regions (12) which are provided overlying a P-type common collector region (11) in a body (10). P-type emitter regions (14) and N-type base contact regions (15) are formed in the base regions such that the base contact regions have a doping level higher than the doping level of the base regions and each base regions is shared by at least two bipolar transistors (20). An independent claim is also included for a cell array manufacturing process.

    10.
    发明专利
    未知

    公开(公告)号：DE60218685D1

    公开(公告)日：2007-04-19

    申请号：DE60218685

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  GASTALDI ROBERTO ,  VENDRAME LORIS ,  BENVENUTI AUGUSTO ,  LOWREY TYLER

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: An array of cells is made by implanting a doping agent of a first conductivity type to first portions of active area regions through first openings of an insulating layer to form second conduction regions; implanting a doping agent of second conductivity type to second portions of the active area regions through second openings of the insulating layer to form control contact regions; and forming storage components on top of the body. Manufacture of an array of cells includes providing a body (10) of semiconductor material of a first conductivity type; implanting, in the body, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conductive region, active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thus forming, in the active area regions second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thus forming control contact regions (15) of the second conductivity type and a second doping level higher than the first doping level; and forming storage components (24) on top of the body. Each control contact region forms, together with the second conduction region and the common conduction region, a selection bipolar transistor (20). Each storage component has a terminal connected to a respective second conduction region. It defines, together with the bipolar transistor, a cell of the cell array.

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