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    1.
    发明专利
    未知

    公开(公告)号：DE60218685T2

    公开(公告)日：2007-11-15

    申请号：DE60218685

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  GASTALDI ROBERTO ,  VENDRAME LORIS ,  BENVENUTI AUGUSTO ,  LOWREY TYLER

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: An array of cells is made by implanting a doping agent of a first conductivity type to first portions of active area regions through first openings of an insulating layer to form second conduction regions; implanting a doping agent of second conductivity type to second portions of the active area regions through second openings of the insulating layer to form control contact regions; and forming storage components on top of the body. Manufacture of an array of cells includes providing a body (10) of semiconductor material of a first conductivity type; implanting, in the body, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conductive region, active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thus forming, in the active area regions second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thus forming control contact regions (15) of the second conductivity type and a second doping level higher than the first doping level; and forming storage components (24) on top of the body. Each control contact region forms, together with the second conduction region and the common conduction region, a selection bipolar transistor (20). Each storage component has a terminal connected to a respective second conduction region. It defines, together with the bipolar transistor, a cell of the cell array.

    2.
    发明专利
    未知

    公开(公告)号：DE60218685D1

    公开(公告)日：2007-04-19

    申请号：DE60218685

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  GASTALDI ROBERTO ,  VENDRAME LORIS ,  BENVENUTI AUGUSTO ,  LOWREY TYLER

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: An array of cells is made by implanting a doping agent of a first conductivity type to first portions of active area regions through first openings of an insulating layer to form second conduction regions; implanting a doping agent of second conductivity type to second portions of the active area regions through second openings of the insulating layer to form control contact regions; and forming storage components on top of the body. Manufacture of an array of cells includes providing a body (10) of semiconductor material of a first conductivity type; implanting, in the body, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conductive region, active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thus forming, in the active area regions second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thus forming control contact regions (15) of the second conductivity type and a second doping level higher than the first doping level; and forming storage components (24) on top of the body. Each control contact region forms, together with the second conduction region and the common conduction region, a selection bipolar transistor (20). Each storage component has a terminal connected to a respective second conduction region. It defines, together with the bipolar transistor, a cell of the cell array.

    READ CIRCUIT
    3.
    发明专利
    READ CIRCUIT 失效

    公开(公告)号：JPH08306190A

    公开(公告)日：1996-11-22

    申请号：JP22355395

    申请日：1995-08-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  ROLANDI PAOLO ,  TORELLI GUIDO

    IPC: G11C11/419 ,  G11C7/06

    Abstract: PROBLEM TO BE SOLVED: To obtain a readout circuit which is used for a memory having a differential cell, and which can be used even in memory reading by a reference cell technique and improves a data read speed and low voltage operations. SOLUTION: A readout circuit has two leg parts SX, DX which are connected to between power source terminals Vdd and Vss , and each of the leg parts series- connects an electronic switch SW1 or SW2; a passive element T1 or T2 forming a voltage amplifier which is feedback-connected to a passive element T2 or T1 in another leg part; and a switch load element L1 or L2 to each other. Each of the passive elements is driven via a high impedance circuit element D1 or D2.

    VOLTAGE GENERATION CIRCUIT AND METHOD FOR OPERATION OF ELECTRIC LOAD ACCORDING TO VOLTAGE
    4.
    发明专利
    VOLTAGE GENERATION CIRCUIT AND METHOD FOR OPERATION OF ELECTRIC LOAD ACCORDING TO VOLTAGE 失效

    公开(公告)号：JPH0883493A

    公开(公告)日：1996-03-26

    申请号：JP23811794

    申请日：1994-09-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  GASTALDI ROBERTO ,  MALCOVATI PIERO ,  TORELLI GUIDO

    IPC: G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  H03K19/0175

    Abstract: PURPOSE: To obtain a voltage generation in a wide range and high reliability by a method wherein positive and negative voltages are generated by a voltage booster circuit and there are provided two 3-state logic gate circuits and additional 3-state logic gate circuit for operating a phase of a charge pump circuit incorporated in a booster. CONSTITUTION: Switch circuits (FFT1 to 6) comprise a 3-state logic gate circuit, boosters 7, 8 have command terminals ϕ1 , ϕ2 , a VDD terminal and a ground terminal, and when VDD is +5V, +10.5V and -10.5V. A booster 9 biases a substrate of a CMOS element of the booster 8. These are connected in a predetermined manner and gate capacitance C1 of a memory cell serves as a load. If a booster voltage is not acquired for the booster, an output is floated and the other boosters are nonactivated so as to occupy priority in common node control freely. With this structure, both positive and negative voltages for operating the memory cell via a control gate terminal are generated, an electrical load is operated, and selection in a wide IC technology and high reliability are obtained.

    Using bit specific reference level to read memory
    5.
    发明专利
    Using bit specific reference level to read memory 有权
    使用位特定参考电平读取存储器

    公开(公告)号：JP2006286180A

    公开(公告)日：2006-10-19

    申请号：JP2006090752

    申请日：2006-03-29

    Applicant: Ovonyx Inc ,  オヴォニクス,インコーポレイテッド

    Inventor： LOWREY TYLER ,  PARKINSON WARD D ,  BEDESCHI FERDINANDO ,  RESTA CLAUDIO ,  GASTALDI ROBERTO ,  CASAGRANDE GIULIO

    IPC: G11C13/00

    CPC classification number: G11C7/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    Abstract: PROBLEM TO BE SOLVED: To provide a method or the like capable of creating a reading window or a reading margin more independent of the variations between bits over an arbitrary array, group or block of memory cells. SOLUTION: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种能够创建读取窗口或读取余量的方法，该方法更加独立于存储器单元的任意阵列，组或块之间的位之间的变化。 解决方案：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 在一些实施例中，可以改善所得到的读取窗口或边缘。 版权所有（C）2007，JPO＆INPIT

    8.
    发明专利
    未知

    公开(公告)号：DE69516402T2

    公开(公告)日：2000-11-02

    申请号：DE69516402

    申请日：1995-07-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C11/56

    Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.

    9.
    发明专利
    未知

    公开(公告)号：DE69514783T2

    公开(公告)日：2000-06-08

    申请号：DE69514783

    申请日：1995-03-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  DANIELE VINCENZO ,  GASTALDI ROBERTO ,  MANSTRETTA ALESSANDRO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00

    Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).

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