公开(公告)号：JPH0750398A

公开(公告)日：1995-02-21

申请号：JP4720994

申请日：1994-03-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: PURPOSE: To prevent the occurrences of stress in the drain terminal of an unselected memory cell in a selected bit line by biasing a positive voltage with respect to the drain terminal of the unselected memory cell for a substrate region and by making the source terminal remain floating. CONSTITUTION: This memory array is provided with a drain region 29 arranged into rows and columns and connected to each of bit lines BL, a source region 30 connected to each source line 24, a control gate region connected to each word line WL, and a large number of memory cells 21 each having a substrate region 28 housing the drain and source regions. A drain terminal of an unselected memory cell, which is connected to a selected bit line during a reading step but not connected to the selected word line and is not connected to the source terminal of the selected memory cell, is biased with a positive voltage with respect to the substrate region 28. The source terminal is kept floating.

公开(公告)号：JPH06224377A

公开(公告)日：1994-08-12

申请号：JP24002693

申请日：1993-09-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide an integrated device in which an LDD structure is partially overlapped on a gate region on a low-doped region. CONSTITUTION: An integrated device is provided with a first polycrystalline silicon layer 12, having a first length in a first direction, an insulating layer 13, and a gate region 18 consisting of a second polycrystalline silicon layer and a third polycrystalline silicon layer on a substrate 2. Also, this device is provided with first substrate regions 37 and 38 and second substrate regions 26 and 29 buried in the substrate under the first polycrystalline silicon layer 12. Moreover, the insulating layer 13 provides an insulating part with a prescribed width in a second direction vertical to a first direction, and the gate region is electrically and directly brought into contact with the first polycrystalline silicon layer in at least one part extended from the insulating part to the second direction of the gate region.

公开(公告)号：JPH115820A

公开(公告)日：1999-01-12

申请号：JP11872498

申请日：1998-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CEROFOLINI GIANFRANCO ,  DE SANTI GIORGIO ,  CRISENZA GIUSEPPE

IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To obtain a dielectric film suitable for use between laminated conductive layers in integrated circuit and provide a method for producing the dielectric film. SOLUTION: A laminated insulating film between laminated conductive layers constituting mutual connection of integrated circuit is constituted by grafting an organic monomer onto an aerogel comprising an inorganic oxide by impulse of an inactive ion and then integrating the organic monomer into the aerogel in order to partially pack many pores of the inorganic aerogel. A composite dielectric substance has a satisfactory thermal budget which is thermally stable. This method for producing the aerogel film comprises spinning a precursor compound solution on a wafer and then, carrying out supercritical solvent extraction in a spinning chamber.

公开(公告)号：JPH0750397A

公开(公告)日：1995-02-21

申请号：JP4720894

申请日：1994-03-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To eliminate errors by reducing the number of memory cells which are excessively erased. CONSTITUTION: A memory array 20 is provided with control transistors 23 of a number of sections regarding sections 22 of memory cells 21. The control transistor of each section is an NMOS transistor, which has a drain terminal connected to a control bit line (BLP) of the transistor. Each control transistor for each section is related to a row part of the memory array. A control gate connected to each word line(WL) and a source region, connected to a source region in the memory cell in the same row and the same section, are presented.

公开(公告)号：DE69325442D1

公开(公告)日：1999-07-29

申请号：DE69325442

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: To reduce the number of depleted cells (21) and the errors caused thereby, the memory array (20) comprises a number of groups of control transistors (23) relative to respective groups (22) of memory cells. The control transistors (23) of each group are NMOS transistors having the drain terminal connected to its own control line (BLP), and each of the control transistors of one group is relative to a row portion of the memory array (20): More specifically, each control transistor (23) presents the control gate connected to the respective word line (WL), and the source region connected to the source region of the cells (21) in the same row and in the same group (22).

公开(公告)号：DE69227772T2

公开(公告)日：1999-06-24

申请号：DE69227772

申请日：1992-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/41

Abstract: A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).

公开(公告)号：DE69325443T2

公开(公告)日：2000-01-27

申请号：DE69325443

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: To reduce the read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. In this way, the threshold voltage of the above cells (the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to the "body effect", whereby the threshold voltage depends, among other things, on the voltage drop between the cell terminal operating as the source and the substrate, and increases alongside an increase in the voltage drop.

公开(公告)号：DE69705387T2

公开(公告)日：2001-10-11

申请号：DE69705387

申请日：1997-04-28

Applicant: ST MICROELECTRONICS SRL

Inventor： CEROFOLINI GIANFRANCO ,  DE SANTI GIORGIO ,  CRISENZA GIUSEPPE

IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is composed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

公开(公告)号：DE69325443D1

公开(公告)日：1999-07-29

申请号：DE69325443

申请日：1993-03-18

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

Abstract: To reduce the read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. In this way, the threshold voltage of the above cells (the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to the "body effect", whereby the threshold voltage depends, among other things, on the voltage drop between the cell terminal operating as the source and the substrate, and increases alongside an increase in the voltage drop.

公开(公告)号：DE69227772D1

公开(公告)日：1999-01-14

申请号：DE69227772

申请日：1992-09-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CRISENZA GIUSEPPE ,  CLEMENTI CESARE

IPC: H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L21/28 ,  H01L29/41

Abstract: A method comprising the steps of depositing a first (12) and second (17) polysilicon layer, separated by an oxide layer (13); selectively etching the second polysilicon layer (17) to form first gate regions (18); forming first substrate regions (26, 29) in the substrate (2) and laterally in relation to the first gate regions; selectively etching the first polysilicon layer (12) to form second gate regions of a length greater than the first gate regions (18); and forming in the substrate, laterally in relation to the second gate regions (12) and partially overlapping the first substrate regions (26, 29), second substrate regions (37, 38) of a higher doping level than the first substrate regions (26, 29).