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    Electrostatic discharge protective network
    1.
    发明专利
    Electrostatic discharge protective network 审中-公开
    静电放电保护网络

    公开(公告)号：JPH11274319A

    公开(公告)日：1999-10-08

    申请号：JP37471898

    申请日：1998-12-28

    Applicant: St Microelectronics Srl ,  エスティマイクロエレクトロニクス・ソチエタ・ア・レスポンサビリタ・リミタータ

    Inventor： COLOMBO PAOLO ,  MULATTI JACOPO ,  CAMPARDO GIOVANNI ,  MACCARRONE MARCO ,  ANNUNZIATA ROBERTO

    IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

    CPC classification number: H01L27/0259 ,  H01L27/0251

    Abstract: PROBLEM TO BE SOLVED: To provide an electrostatic discharge(ESD) protective network, which has such structural and functional features that meet the nonsensitive requirements of a substrate for noise and accordingly, can isolate various circuit blocks from noise or disturbance. SOLUTION: An ESD protective network incorporates first ESD protective parts 14 for the input stage of a circuit structure, second ESD protective parts 5 for the output stage of the circuit structure, at least one ESD protective parts B0 between a primary power source Vcc and a primary ground GND, and at least one EDGE protective parts B between a secondary power source Vcc- IO and a secondary ground GND- IO, and the first and second protective parts 15 and 5 commonly use the input-output terminal 20 of an integrated circuit structure.

    Abstract translation: 要解决的问题：提供一种静电放电（ESD）保护网络，其具有满足基板对噪声的不敏感要求的结构和功能特征，因此可以将各种电路块与噪声或干扰隔离开来。 解决方案：ESD保护网络包括用于电路结构的输入级的第一ESD保护部件14，用于电路结构的输出级的第二ESD保护部件5，主电源Vcc和 主接地GND以及次级电源Vcc-IO和次级地GND-IO之间的至少一个EDGE保护部分B，并且第一和第二保护部分15和5通常使用集成电路的输入 - 输出端子20 结构体。

    Method for reforming effect of esd protection of semiconductor circuit structure, and circuit structure thereof
    2.
    发明专利
    Method for reforming effect of esd protection of semiconductor circuit structure, and circuit structure thereof 审中-公开
    用于改善半导体电路结构的ESD保护效果的方法及其电路结构

    公开(公告)号：JPH11274166A

    公开(公告)日：1999-10-08

    申请号：JP37004798

    申请日：1998-12-25

    Applicant: St Microelectronics Srl ,  エスティマイクロエレクトロニクス・ソチエタ・ア・レスポンサビリタ・リミタータ

    Inventor： COLOMBO PAOLO ,  CAMERLENGHI EMILIO

    IPC: H01L29/73 ,  H01L21/331 ,  H01L27/02 ,  H01L29/732 ,  H01L29/735

    CPC classification number: H01L29/735 ,  H01L27/0259

    Abstract: PROBLEM TO BE SOLVED: To improve the ESD protection of an electronic element.
    SOLUTION: This method and circuit structure is for reforming the effect of protection of an ESD in circuit structure made in a semiconductor substrate, covered with the epitaxial layer 3 which is equipped with at least one ESD protecting lateral bipolar transistor 5 formed at the surface of the epitaxial layer 3, and a circuit structure so as to form a well 4 which is isolated from a substrate 2 under the transistor 5. The bipolar transistor 5 is completely isolated from the substrate 2 by first (10) and second (11) n-type wells which extend downward from the epitaxial layer 3 to the embedded well 4 and in contact with it.
    COPYRIGHT: (C)1999,JPO

    Abstract translation: 要解决的问题：改善电子元件的ESD保护。 解决方案：该方法和电路结构用于重整在半导体衬底中形成的电路结构中ESD保护的效果，该半导体衬底被外延层3覆盖，外延层3配备有至少一个ESD保护侧面双极晶体管5， 外延层3和电路结构，以形成与晶体管5下面的衬底2隔离的阱4.双极晶体管5通过第一（10）和第二（11）n与衬底2完全隔离 型阱，其从外延层3向下延伸到嵌入阱4并与其接触。

    Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate
    3.
    发明授权
    Method and a circuit for improving the effectiveness of ESD protection in circuit structures formed in a semiconductor substrate 有权
    用于提高在半导体衬底中形成的电路结构中的ESD保护的有效性的方法和电路

    公开(公告)号：US6372597B2

    公开(公告)日：2002-04-16

    申请号：US83713701

    申请日：2001-04-17

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COLOMBO PAOLO ,  CAMERLENGHI EMILIO

    IPC: H01L29/73 ,  H01L21/331 ,  H01L27/02 ,  H01L29/732 ,  H01L29/735

    CPC classification number: H01L29/735 ,  H01L27/0259

    Abstract: A method and a related circuit structure are described for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate overlaid with an epitaxial layer and including at least one ESD protection lateral bipolar transistor realized in the surface of the epitaxial layer. The method consists of forming under the transistor an isolating well that isolates the transistor from the substrate. Advantageously, the transistor can be fully isolated from the substrate by first and second N wells which extend from the surface of the epitaxial layer down to and in contact with the buried well.

    Abstract translation: 描述了一种方法和相关的电路结构，用于提高在覆盖有外延层的半导体衬底中实现的电路结构中的ESD保护的有效性，并且包括在外延层的表面中实现的至少一个ESD保护横向双极晶体管。 该方法包括在晶体管下形成将晶体管与衬底隔离的隔离阱。 有利的是，晶体管可以通过第一和第二N阱从衬底完全隔离，该N阱从外延层的表面向下延伸到埋入阱并与其接触。

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