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公开(公告)号：ITTO990291A1
公开(公告)日：2000-10-13
申请号：ITTO990291
申请日：1999-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONDEMI CARMELO , LA PLACA MICHELE , MARTINES IGNAZIO
Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.
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公开(公告)号：ITTO990290A1
公开(公告)日：2000-10-13
申请号：ITTO990290
申请日：1999-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONDEMI CARMELO , LA PLACA MICHELE , MARTINES IGNAZIO
IPC: G11C16/28
Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.
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公开(公告)号：ITVA20000015D0
公开(公告)日：2000-05-30
申请号：ITVA20000015
申请日：2000-05-30
Applicant: ST MICROELECTRONICS SRL
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Patent Agency Ranking
公开(公告)号：DE60222891T2
公开(公告)日：2008-07-24
申请号：DE60222891
申请日：2002-08-13
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA , CONDEMI CARMELO
Abstract: The nonvolatile storage device (1) is made up of a memory array (2) divided into a plurality of data-storage units (19a) and a plurality of redundancy-storage units (19b) for replacing respective failed data-storage units. A control unit (16) detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit (15) having a plurality of volatile-memory elements (22) connected through a sequential daisy-chain connection. A nonvolatile memory unit (CAM 18) stores, in a nonvolatile way, the redundancy information through a data bus (11), connected both to the redundancy-detection unit (15) and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit (15) transfers the addresses of the failed data-storage unit (19a) to the nonvolatile memory unit (18) for their nonvolatile storage.
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公开(公告)号：IT1307687B1
公开(公告)日：2001-11-14
申请号：ITTO990291
申请日：1999-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONDEMI CARMELO , LA PLACA MICHELE , MARTINES IGNAZIO
Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.
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公开(公告)号：IT1307686B1
公开(公告)日：2001-11-14
申请号：ITTO990290
申请日：1999-04-13
Applicant: ST MICROELECTRONICS SRL
Inventor： CONDEMI CARMELO , LA PLACA MICHELE , MARTINES IGNAZIO
IPC: G11C16/28
Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.
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公开(公告)号：DE60222891D1
公开(公告)日：2007-11-22
申请号：DE60222891
申请日：2002-08-13
Applicant: ST MICROELECTRONICS SRL
Inventor： DE AMBROGGI LUCA , CONDEMI CARMELO
Abstract: The nonvolatile storage device (1) is made up of a memory array (2) divided into a plurality of data-storage units (19a) and a plurality of redundancy-storage units (19b) for replacing respective failed data-storage units. A control unit (16) detects the functionality of the data-storage units and, in case of failure, enables a redundancy-detection unit (15) having a plurality of volatile-memory elements (22) connected through a sequential daisy-chain connection. A nonvolatile memory unit (CAM 18) stores, in a nonvolatile way, the redundancy information through a data bus (11), connected both to the redundancy-detection unit (15) and to the nonvolatile memory unit; in the event of failure, the redundancy-detection unit (15) transfers the addresses of the failed data-storage unit (19a) to the nonvolatile memory unit (18) for their nonvolatile storage.
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公开(公告)号：ITVA20000015A1
公开(公告)日：2001-11-30
申请号：ITVA20000015
申请日：2000-05-30
Applicant: ST MICROELECTRONICS SRL
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