公开(公告)号：JP2000200844A

公开(公告)日：2000-07-18

申请号：JP37471499

申请日：1999-12-28

Applicant: ST MICROELECTRONICS SRL

Inventor： FONTANA GABRIELLA ,  PIVIDORI LUCA

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To prevent a silicide film from being formed on a doped region inside a semiconductor substrate. SOLUTION: A step is provided, where a dielectric film 6 is formed so as to cover all regions which require a silicification treatment before a silicifying step is carried out, and a polysilicon part 5 is not covered with the dielectric film 6. A region on the left polysilicon part 5 is subjected to a preferable silicification treatment without introducing an additional masking step.

公开(公告)号：DE69636738D1

公开(公告)日：2007-01-11

申请号：DE69636738

申请日：1996-12-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  CAPRARA PAOLO ,  FONTANA GABRIELLA

IPC: H01L21/28 ,  H01L27/00 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: The present invention relates to a process for creation of contacts (25) in semiconductor electronic devices and in particular on bit lines of non-volatile memories with cross-point structure comprising memory cell matrices in which the bit lines are parallel unbroken diffusion strips (12) extending along a column of the matrix with the contacts (25) being provided through associated contact apertures (24) defined through a dielectric layer (21) deposited over a contact region defined on a semiconductor substrate (11) at one end of the bit lines (12). The process calls for a step of implantation and following diffusion of contact areas (22) provided in the substrate (11) at opposite sides of each bit line (12) to be contacted to widen the area designed to receive the contacts (25).

公开(公告)号：DE69832083D1

公开(公告)日：2005-12-01

申请号：DE69832083

申请日：1998-12-29

Applicant: ST MICROELECTRONICS SRL

Inventor： FONTANA GABRIELLA ,  PIVIDORI LUCA

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L21/8239

Abstract: A selective silicidation process for electronic devices (1) integrated on a semiconductor substrate (2), said devices (1) comprising a plurality of active elements (3) formed with gate regions (4) which comprise at least one polysilicon layer (5), comprises the following steps: depositing a dielectric layer (6) over the entire surface of the semiconductor; removing said dielectric layer (6) to expose the polysilicon layer (5) of said gate regions (4); depositing a layer of a transition metal (7); subjecting the transition metal layer to a thermal treatment for selectively reacting it with the polysilicon layers and producing a silicide layer (8) over said gate regions (4).