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    MANUFACTURE OF INSULATED GATE FIELD EFFECT TRANSISTOR
    1.
    发明专利
    MANUFACTURE OF INSULATED GATE FIELD EFFECT TRANSISTOR 失效

    公开(公告)号：JPH10303140A

    公开(公告)日：1998-11-13

    申请号：JP10956898

    申请日：1998-04-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRATIN LORENZO ,  RIVA CARLO

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

    Abstract: PROBLEM TO BE SOLVED: To reduce the number of implanting processes without giving any damage to a uniform channel having a fixed length. SOLUTION: A method for manufacturing an insulated gate field effect transistor includes a process for deciding the boundary of an active area on a substrate, a process for forming gate electrodes 82, 83, and 88 insulated from the substrate on the active area, and process for forming a source area and a drain area by performing implanting ions into the upper surface of the substrate several times by using an ion beam for doping by using the gate electrodes as a mask. The direction of the implanting beam is defined by the tilt angle of the ion beam from the upper surface of the substrate and the directions (45 deg., 135 deg., 225 deg., and 315 deg.) of the ion beam from a reference line 80 on the substrate. The widths of the gate electrode strips 82, 83, and 88 are decided in accordance with the directions of the strips from the reference line 80 and the direction of the ion beam in the designing process.

    2.
    发明专利
    未知

    公开(公告)号：DE69737966D1

    公开(公告)日：2007-09-13

    申请号：DE69737966

    申请日：1997-04-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRATIN LORENZO ,  RIVA CARLO

    IPC: H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

    Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45 DEG , 135 DEG , 225 DEG , 315 DEG ) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

    3.
    发明专利
    未知

    公开(公告)号：DE69723044D1

    公开(公告)日：2003-07-31

    申请号：DE69723044

    申请日：1997-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALEGARI CAMILLA ,  CARRARA ANNA ,  FRATIN LORENZO ,  RIVA CARLO

    IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    Abstract: A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30). In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).

    6.
    发明专利
    未知

    公开(公告)号：DE69630944D1

    公开(公告)日：2004-01-15

    申请号：DE69630944

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRATIN LORENZO ,  RIVA CARLO

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8247

    Abstract: A MOS transistor (1) capable of withstanding relatively high voltages is of a type integrated on a region (3) included in a substrate of semiconductor material, having conductivity of a first type (N) and comprising a channel region (7) intermediate between a first active region of source (4) and a second active region of drain (5). Both these regions (4 and 5) have conductivity of a second type (P) and extend from a first surface (6) of the substrate. The transistor (1) also has a gate which comprises at least a first polysilicon layer (8) overlying the first surface (6) at at least said channel region (7), to which it is coupled capacitively through a gate oxide layer (9). According to the invention, the first polysilicon layer (8) includes a mid-portion (13) which only overlies said channel region (7) and has a first total conductivity (C1) of said first type (N), and a peripheral portion (14) with a second total conductivity (C2) differentiated from said first total conductivity (C1), which peripheral portion partly overlies said source and drain active regions (4 and 5) toward said channel region (7).

    7.
    发明专利
    未知

    公开(公告)号：DE69413960T2

    公开(公告)日：1999-04-01

    申请号：DE69413960

    申请日：1994-07-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

    IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

    Abstract: A nonvolatile memory (40) having a cell (31) comprising an N type source region (24) and drain region (12) embedded in a P type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

    9.
    发明专利
    未知

    公开(公告)号：DE69723044T2

    公开(公告)日：2004-05-06

    申请号：DE69723044

    申请日：1997-01-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALEGARI CAMILLA ,  CARRARA ANNA ,  FRATIN LORENZO ,  RIVA CARLO

    IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

    Abstract: A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30). In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).

    10.
    发明专利
    未知

    公开(公告)号：DE69413960D1

    公开(公告)日：1998-11-19

    申请号：DE69413960

    申请日：1994-07-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

    IPC: H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00

    Abstract: A nonvolatile memory (40) having a cell (31) comprising an N type source region (24) and drain region (12) embedded in a P type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

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