公开(公告)号：JPH0745730A

公开(公告)日：1995-02-14

申请号：JP2281894

申请日：1994-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To increase the reliability and life of a storage circuit, while reducing the deterioration of a tunnel oxide. CONSTITUTION: A double-level polysilicon EEPROM memory cell with a control gate 15 that is connected in series with a selective transistor 14 and is located at the upper layer of a floating gate 12 and a dielectric layer 11 between the gates has a region 10, consisting of an n -type region 18 and an n -type region.

公开(公告)号：JPH10303140A

公开(公告)日：1998-11-13

申请号：JP10956898

申请日：1998-04-20

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RIVA CARLO

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To reduce the number of implanting processes without giving any damage to a uniform channel having a fixed length. SOLUTION: A method for manufacturing an insulated gate field effect transistor includes a process for deciding the boundary of an active area on a substrate, a process for forming gate electrodes 82, 83, and 88 insulated from the substrate on the active area, and process for forming a source area and a drain area by performing implanting ions into the upper surface of the substrate several times by using an ion beam for doping by using the gate electrodes as a mask. The direction of the implanting beam is defined by the tilt angle of the ion beam from the upper surface of the substrate and the directions (45 deg., 135 deg., 225 deg., and 315 deg.) of the ion beam from a reference line 80 on the substrate. The widths of the gate electrode strips 82, 83, and 88 are decided in accordance with the directions of the strips from the reference line 80 and the direction of the ion beam in the designing process.

公开(公告)号：JPH04359477A

公开(公告)日：1992-12-11

申请号：JP18255591

申请日：1991-07-23

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a single polysilicon level EPROM cell comprising a partially superposed floating gate on a double dope source and a drain region, requiring no additional mask, within a process range for obtaining an LDD or DDD type transistor. CONSTITUTION: With regions 7, 8, and 9 of P-type semiconductor substrate N type implanted at the same time, a control gate 9, a high dope source region 7, and a drain region 8 are formed to constitute a channel region 4. After oxide growth (11), (12), sticking and formation are performed with a polysilicon layer 10, and a region 1 constitutes a floating gate which, while formed on the control gate 9 and the channel region 4, is partially superposed on the source region 7 and the drain region 8.

公开(公告)号：DE69739250D1

公开(公告)日：2009-03-26

申请号：DE69739250

申请日：1997-12-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  RIVA CARLO

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/105 ,  H01L29/417 ,  H01L29/45

Abstract: An HV transistor (2) integrated in a semiconductor substrate (1) with a first type of conductivity, comprising a gate region (12) included between corresponding drain (16) and source (17) regions, and being of the type wherein at least said drain region (16) is lightly doped with a second type of conductivity. The drain region (16) comprises a contact region (7) with the second type of conductivity but being more heavily doped, from which a contact pad (21) stands proud.

公开(公告)号：DE69723044D1

公开(公告)日：2003-07-31

申请号：DE69723044

申请日：1997-01-31

Applicant: ST MICROELECTRONICS SRL

Inventor： CALEGARI CAMILLA ,  CARRARA ANNA ,  FRATIN LORENZO ,  RIVA CARLO

IPC: H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

Abstract: A process for the formation of a device edge morphological structure (30) for protecting and sealing peripherally an electronic circuit integrated in a major surface (5) of a substrate of semiconductor material (6) is of the type that calls for formation above the major surface (5) of at least one dielectric multilayer (20) comprising a layer of amorphous planarizing material (22) having a continuous portion extending between two contiguous areas with a more internal first area (3') and a more external second area (4') in the morphological structure (30). In accordance with the present invention inside the device edge morphological structure (30) in the substrate (6) is formed an excavation on the side of the major surface (5) the more internal first area (3') of the morphological structure (30) in a zone in which is present the continuous portion of the dielectric multilayer (20).

公开(公告)号：DE69528971D1

公开(公告)日：2003-01-09

申请号：DE69528971

申请日：1995-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： CLEMENTI CESARE ,  GHIDINI GABRIELLA ,  RIVA CARLO

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115

公开(公告)号：DE69521041T2

公开(公告)日：2001-11-22

申请号：DE69521041

申请日：1995-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/06

公开(公告)号：DE69521041D1

公开(公告)日：2001-06-28

申请号：DE69521041

申请日：1995-08-02

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RAVAZZI LEONARDO ,  RIVA CARLO

IPC: G11C5/14 ,  G11C16/30 ,  G11C16/06

公开(公告)号：DE69737966D1

公开(公告)日：2007-09-13

申请号：DE69737966

申请日：1997-04-21

Applicant: ST MICROELECTRONICS SRL

Inventor： FRATIN LORENZO ,  RIVA CARLO

IPC: H01L21/265 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

Abstract: The method described provides for the following steps: delimiting active areas (81) on a substrate, forming gate electrodes (82, 83, 88) insulated from the substrate on the active areas, and subjecting the front surface of the substrate to several implantation steps with doping ion beams to form source and drain regions with the use of the gate electrodes as masks. The direction of the implantation beam is defined by an angle of inclination to the front surface and by an orientation (45 DEG , 135 DEG , 225 DEG , 315 DEG ) to a reference line (80) on the front surface. To avoid performing numerous implantation steps without foregoing channels of uniform and constant length (L''), the widths of the gate electrode strips (82, 83, 88) are determined at the design stage in dependence on the orientation of the strips to the reference line (80) and on the orientation of the directions of the implant beams.

公开(公告)号：DE69032937D1

公开(公告)日：1999-03-18

申请号：DE69032937

申请日：1990-07-24

Applicant: ST MICROELECTRONICS SRL

Inventor： MAURELLI ALFONSO ,  RIVA CARLO

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82 ,  G11C16/04

Abstract: The process provides for the simultaneous N+ type implantation of areas (7, 8, 9) of a semiconductor substrate of type P for the formation of a control gate (9) and of highly doped regions of source (7) and drain (8), defining a channel region (4). After oxide growth (11, 12) there is executed the deposition and the definition of a polysilicon layer (10), one region of which constitutes a floating gate above the control gate (9) and the channel region (4) and partially superimposed over the regions of source (7) and drain (8).