公开(公告)号：JPH07106604A

公开(公告)日：1995-04-21

申请号：JP20366994

申请日：1994-08-29

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: PURPOSE: To manufacture an integrated voltage control/stabilizing element having stable clamp voltage without additionally providing a manufacturing process in a flash EEPROM memory device. CONSTITUTION: This manufacturing method contains a process with which an N-type low doped well 2 is formed in a single crystal silicon substrate 1, a process with which an active region 4 is formed on the surface of the N-type well 2, a process with which a thin gate oxide layer is grown on the active region 4, and a process with which an N-type region 6 is formed by implanting the first high dosage of N-type dopant into the N-type well 2. Also, a process with which an N contact region 7 is obtained against both of the N-type well 2 and the N-type region 6 by implanting the N-type dopant of the second high dose higher than the first high dose, and a process with which a P region 8 is formed by implanting the P-type dopant of the third high dose, which is higher than the first high dose, into the N-type region 6, are provided.

公开(公告)号：JP2000022003A

公开(公告)日：2000-01-21

申请号：JP12951999

申请日：1999-05-11

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  GHEZZI PAOLO

IPC: G11C16/06 ,  H01L21/8246 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure capable of integrating ROM memory cells into the memory cell matrix to be electrically written in formed by self-aligned sourcing process. SOLUTION: A memory cell matrix structure formed by self aligning with a field oxide layer 3 and an upper side poly Si is equipped with at least one each of the first ROM cell 6 and at least one each of the second ROM cell 5 in relation to the rows and columns of a matrix as well as a P type Si substrate 9 whereon the first and second separating regions are formed for making the first ROM cell 6 specify the fine columns, a gate element 2 traversing and extending the fine columns from one side of the first separating region to one side of the second separating region, the third and fourth n type regions 11, 12 as well as the field oxide region 3 blocking the formation of a conductive channel on the substrate 9, besides, the field oxide region does not exists in the second ROM cell 5 although in the same structure as that of the first ROM cell 6.

公开(公告)号：DE69942273D1

公开(公告)日：2010-06-02

申请号：DE69942273

申请日：1999-07-21

Applicant: ST MICROELECTRONICS SRL

Inventor： VENDRAME LORIS ,  GHEZZI PAOLO

IPC: H01L27/105 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/732

Abstract: This invention refers to a bipolar transistor obtained by means of a process for CMOS devices of non volatile memories, and in particular to an integrated circuit comprising a vertical transistor at high gain. Besides it refers to a building process of a bipolar transistor obtained by means a process for CMOS devices of non volatile memories. In one embodiment the integrated circuit obtained by means of a process for CMOS devices of non volatile memories comprises a semiconductor substrate (2) having a first type of conductivity, a pMOS transistor formed above said substrate (2), a nMOS transistor formed above said substrate (2), a bipolar transistor (1) comprising: a buried semiconductor layer (4) having a second type of conductivity placed at a prefixed depth from the surface of said bipolar transistor (1), a isolation semiconductor region (5) having a second type of conductivity in direct contact with said buried semiconductor layer (4) and suitable for delimiting a portion of said substrate (2) forming a base region (3), a emitter region (8) of said transistor (1) formed within said base region (3) having a second type of conductivity, a base contact region (6) of said transistor (1) formed within said base region (3) having a first type of conductivity, a collector contact region (7) of said transistor (1) formed within said isolation semiconductor region (5) having a second type of conductivity, characterised in that said base region (3) has a doping concentration included between 10 and 10 atoms/cm .

公开(公告)号：DE69322384T2

公开(公告)日：1999-05-12

申请号：DE69322384

申请日：1993-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: A process for the manufacture of a zener-diode as an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well (2) on a single-crystal silicon substrate (1); a step of formation of an active area (4) on the surface of said N type well (2); a step of growth of a thin gate oxide layer (5) over said active area (4); a step of implantation of a first heavy dose of N type dopant into said N type well (2) to obtain an N type region (6; 18; 19); a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region (6; 18) to obtain an N+ contact region (7; 20) to both the N type well (2) and said N type region (6; 18; 19); a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region (6; 19) to form a P+ region (8; 21). The N+ region (7; 20) is of annular shape. The zener-diode can also be gated. All manufacturing steps for the zener-diode correspond to manufacturing steps of the flash EEPROM memory device.

公开(公告)号：DE69322384D1

公开(公告)日：1999-01-14

申请号：DE69322384

申请日：1993-09-10

Applicant: ST MICROELECTRONICS SRL

Inventor： GHEZZI PAOLO ,  MAURELLI ALFONSO

IPC: H01L21/8247 ,  H01L21/329 ,  H01L27/06 ,  H01L27/115 ,  H01L29/866

Abstract: A process for the manufacture of a zener-diode as an integrated voltage limiter and stabilizer component in a flash EEPROM memory device comprises a step of formation of an N type lightly doped well (2) on a single-crystal silicon substrate (1); a step of formation of an active area (4) on the surface of said N type well (2); a step of growth of a thin gate oxide layer (5) over said active area (4); a step of implantation of a first heavy dose of N type dopant into said N type well (2) to obtain an N type region (6; 18; 19); a step of implantation of a second heavy dose, higher than said first heavy dose, of N type dopant into said N type region (6; 18) to obtain an N+ contact region (7; 20) to both the N type well (2) and said N type region (6; 18; 19); a step of implantation of a third heavy dose, higher than said first heavy dose, of P type dopant into said N type region (6; 19) to form a P+ region (8; 21). The N+ region (7; 20) is of annular shape. The zener-diode can also be gated. All manufacturing steps for the zener-diode correspond to manufacturing steps of the flash EEPROM memory device.