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    1.
    发明专利
    未知

    公开(公告)号：DE60306892T2

    公开(公告)日：2007-08-30

    申请号：DE60306892

    申请日：2003-05-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BORTESI LUCA ,  VENDRAME LORIS ,  BOGLIOLO ALESSANDRO

    IPC: G01R27/26 ,  G01R31/02 ,  G01R31/28

    Abstract: A method and a corresponding arrangement for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. The method and arrangement solve the problem of short-circuit currents that affects the known test structures, and allow a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

    2.
    发明专利
    未知

    公开(公告)号：DE60218685D1

    公开(公告)日：2007-04-19

    申请号：DE60218685

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  GASTALDI ROBERTO ,  VENDRAME LORIS ,  BENVENUTI AUGUSTO ,  LOWREY TYLER

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: An array of cells is made by implanting a doping agent of a first conductivity type to first portions of active area regions through first openings of an insulating layer to form second conduction regions; implanting a doping agent of second conductivity type to second portions of the active area regions through second openings of the insulating layer to form control contact regions; and forming storage components on top of the body. Manufacture of an array of cells includes providing a body (10) of semiconductor material of a first conductivity type; implanting, in the body, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conductive region, active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thus forming, in the active area regions second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thus forming control contact regions (15) of the second conductivity type and a second doping level higher than the first doping level; and forming storage components (24) on top of the body. Each control contact region forms, together with the second conduction region and the common conduction region, a selection bipolar transistor (20). Each storage component has a terminal connected to a respective second conduction region. It defines, together with the bipolar transistor, a cell of the cell array.

    3.
    发明专利
    未知

    公开(公告)号：DE602004026447D1

    公开(公告)日：2010-05-20

    申请号：DE602004026447

    申请日：2004-09-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEDESCHI FERDINANDO ,  PELLIZZER FABIO ,  BENVENUTI AUGUSTO ,  VENDRAME LORIS ,  ZULIANI PAOLA

    IPC: G11C16/02 ,  G11C11/34

    Abstract: A memory device is proposed. The memory device includes a plurality of memory cells (P,S), wherein each memory cell includes a storage element (P) and a selector (S) for selecting the corresponding storage element during a reading operation or a programming operation. The selector includes a unipolar element (M) and a bipolar element (D;B). The memory device further includes control means (110s) for prevalently enabling the unipolar element during the reading operation or the bipolar element during the programming operation.

    4.
    发明专利
    未知

    公开(公告)号：DE60306892D1

    公开(公告)日：2006-08-31

    申请号：DE60306892

    申请日：2003-05-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BORTESI LUCA ,  VENDRAME LORIS ,  BOGLIOLO ALESSANDRO

    IPC: G01R27/26 ,  G01R31/02 ,  G01R31/28

    Abstract: A method and a corresponding arrangement for measuring the coupling capacitance between two interconnect lines exploits the so-called cross-talk effect and keeps an interconnect line at a constant reference voltage. The method and arrangement solve the problem of short-circuit currents that affects the known test structures, and allow a direct measurement of the coupling capacitance between the two interconnect lines. Capacitance measurements may also be used for determining points of interruption of interconnect lines. When a line is interrupted, the measured coupling capacitance is the capacitance of a single conducting branch. The position of points of interruption of an interconnect line is determined by measuring the coupling capacitance of all segments of the line with a second conducting line.

    5.
    发明专利
    未知

    公开(公告)号：DE60218685T2

    公开(公告)日：2007-11-15

    申请号：DE60218685

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  GASTALDI ROBERTO ,  VENDRAME LORIS ,  BENVENUTI AUGUSTO ,  LOWREY TYLER

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: An array of cells is made by implanting a doping agent of a first conductivity type to first portions of active area regions through first openings of an insulating layer to form second conduction regions; implanting a doping agent of second conductivity type to second portions of the active area regions through second openings of the insulating layer to form control contact regions; and forming storage components on top of the body. Manufacture of an array of cells includes providing a body (10) of semiconductor material of a first conductivity type; implanting, in the body, a common conduction region (11) of the first conductivity type; forming, in the body, above the common conductive region, active area regions (12) of a second conductivity type and a first doping level; forming, on top of the body, an insulating layer having first and second openings (27a, 27b); implanting first portions of the active area regions through the first openings with a doping agent of the first conductivity type, thus forming, in the active area regions second conduction regions of the first conductivity type; implanting second portions of the active area regions through the second openings with a doping agent of the second conductivity type, thus forming control contact regions (15) of the second conductivity type and a second doping level higher than the first doping level; and forming storage components (24) on top of the body. Each control contact region forms, together with the second conduction region and the common conduction region, a selection bipolar transistor (20). Each storage component has a terminal connected to a respective second conduction region. It defines, together with the bipolar transistor, a cell of the cell array.

    6.
    发明专利
    未知

    公开(公告)号：DE69942273D1

    公开(公告)日：2010-06-02

    申请号：DE69942273

    申请日：1999-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VENDRAME LORIS ,  GHEZZI PAOLO

    IPC: H01L27/105 ,  H01L21/8249 ,  H01L29/06 ,  H01L29/732

    Abstract: This invention refers to a bipolar transistor obtained by means of a process for CMOS devices of non volatile memories, and in particular to an integrated circuit comprising a vertical transistor at high gain. Besides it refers to a building process of a bipolar transistor obtained by means a process for CMOS devices of non volatile memories. In one embodiment the integrated circuit obtained by means of a process for CMOS devices of non volatile memories comprises a semiconductor substrate (2) having a first type of conductivity, a pMOS transistor formed above said substrate (2), a nMOS transistor formed above said substrate (2), a bipolar transistor (1) comprising: a buried semiconductor layer (4) having a second type of conductivity placed at a prefixed depth from the surface of said bipolar transistor (1), a isolation semiconductor region (5) having a second type of conductivity in direct contact with said buried semiconductor layer (4) and suitable for delimiting a portion of said substrate (2) forming a base region (3), a emitter region (8) of said transistor (1) formed within said base region (3) having a second type of conductivity, a base contact region (6) of said transistor (1) formed within said base region (3) having a first type of conductivity, a collector contact region (7) of said transistor (1) formed within said isolation semiconductor region (5) having a second type of conductivity, characterised in that said base region (3) has a doping concentration included between 10 and 10 atoms/cm .

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