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    NOR-TYPE ROM PROVIDED WITH LDD CELL
    1.
    发明专利
    NOR-TYPE ROM PROVIDED WITH LDD CELL 失效

    公开(公告)号：JPH0669463A

    公开(公告)日：1994-03-11

    申请号：JP18449093

    申请日：1993-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHIO EMILIO GIAMBATTISTA ,  MERONI GIUSEPPE ,  RE DANILO ,  BALDI LIVIO

    IPC: G11C17/12 ,  H01L21/8238 ,  H01L21/8246 ,  H01L27/092 ,  H01L27/112

    Abstract: PURPOSE: To obtain a ROM matrix whose cell has the junction of diffused parts with concentration gradients by a method wherein ions sufficient to reverse the conductivity-type of a part of a drain region are implanted and diffused and the drain region is decoupled from a channel region. CONSTITUTION: A gate oxide layer 2, a single cell gate electrode 3 and drain regions 4 and 5 are formed in a semiconductor substrate region 1 having the p-type conductivity. A part of the drain area of a programming cell to which a current is not applied is restricted by a photoresist mask M1. Phosphorus ions are diffused through the aperture of the photoresist mask M1 and boron ions are implanted. The conductivity type of a region 6 between programming channel and drain regions is reversed. Then a photoresist mask M2 is formed, drain area of the memory cell is masked and arsenic ions are implanted through the aperture.

    METHOD FOR FORMING CONTACT PLUG BY BLANKET CVD ATTACHMENT AND ETCH BACK
    2.
    发明专利
    METHOD FOR FORMING CONTACT PLUG BY BLANKET CVD ATTACHMENT AND ETCH BACK 失效

    公开(公告)号：JPH04321224A

    公开(公告)日：1992-11-11

    申请号：JP28066491

    申请日：1991-10-01

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  ERRATICO PIETRO

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768

    Abstract: PURPOSE: To secure flatness of a hole and an insulating layer, without decrease of a filler by overetching a 1st metallic substance, so as to remove a residue of a metallic substance present on an unmasked surface. CONSTITUTION: A tungsten peak of a plug 1, which is coplanar with the surface of an insulating layer 2, is completely masked with a cap 5 of resist. After this masking, etching conditions is corrected more preferably over operation under conditions similar to precedent etching-back conditions for decreasing the anisotropy of etching, thereby over-etching a tungsten residue in an RIE plasma, while increasing the selectivity of an insulating substance (oxide) forming a separate layer 2. For this purpose, a 2nd masked etching-back process of tungsten filling for removing the residue is performed in a mixture of F6 , Cl2 , and Ar and/or under a pressure lower than the 1st etching-back step.

    5.
    发明专利
    失效

    公开(公告)号：JPH05259164A

    公开(公告)日：1993-10-08

    申请号：JP31173492

    申请日：1992-11-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO

    IPC: H01L21/285 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52

    Abstract: PURPOSE: To provide a method for forming a metal contact high in stabilization on in an integrate circuit having one or more metal deposited layer. CONSTITUTION: This method forms a metallic contact which is high in stabilization in an integrated circuit, having one or more metals deposited layer, and in a method containing an auxiliary step forming a plurality of contact holes 7 which are substantially flat to a dielectric layer 5 at both ends and respectively open to an intermediate area of a circuit in the dielectric layer 5. This method comprises the steps of (a) forming a first layer 9 of tungsten on the dielectric layer by a chemical vapor growth method to uniformly cover a bottom part and a wall part of the contact hole 7, (b) forming a second layer 11 of aluminum or its alloy on the first layer 9 of tungsten by sputtering to fill the contact hole 7, and (c) removing selectively a specific region of a laminate of the aluminum layer 11 and the tungsten layer 9, so that a plurality of metal wires 13 having a specific shape are formed.

    MATRIX STRUCTURE OF MEMORY CELL AND MANUFACTURE THEREOF
    6.
    发明专利
    MATRIX STRUCTURE OF MEMORY CELL AND MANUFACTURE THEREOF 失效

    公开(公告)号：JP2000022003A

    公开(公告)日：2000-01-21

    申请号：JP12951999

    申请日：1999-05-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  GHEZZI PAOLO

    IPC: G11C16/06 ,  H01L21/8246 ,  H01L27/112

    Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure capable of integrating ROM memory cells into the memory cell matrix to be electrically written in formed by self-aligned sourcing process. SOLUTION: A memory cell matrix structure formed by self aligning with a field oxide layer 3 and an upper side poly Si is equipped with at least one each of the first ROM cell 6 and at least one each of the second ROM cell 5 in relation to the rows and columns of a matrix as well as a P type Si substrate 9 whereon the first and second separating regions are formed for making the first ROM cell 6 specify the fine columns, a gate element 2 traversing and extending the fine columns from one side of the first separating region to one side of the second separating region, the third and fourth n type regions 11, 12 as well as the field oxide region 3 blocking the formation of a conductive channel on the substrate 9, besides, the field oxide region does not exists in the second ROM cell 5 although in the same structure as that of the first ROM cell 6.

    METHOD AND EQUIPMENT FOR SUPPLY OF NEGATIVE PROGRAMMING VOLTAGE TO NONVOLATILE MEMORY CELL
    7.
    发明专利
    METHOD AND EQUIPMENT FOR SUPPLY OF NEGATIVE PROGRAMMING VOLTAGE TO NONVOLATILE MEMORY CELL 失效

    公开(公告)号：JPH07254293A

    公开(公告)日：1995-10-03

    申请号：JP28634994

    申请日：1994-11-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BALDI LIVIO ,  PIO FEDERICO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/12 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    Abstract: PURPOSE: To provide a method, with which a negative programming voltage is supplied to a non-volatile memory cell, suitable for integrated execution. CONSTITUTION: In order to supply the negative programming voltage to the non-volatile memory cell inside a non-volatile memory device, a 1st pole plate A of a capacitor C is connected through 1st switching means TX and TY to a positive high voltage source Vpp. Besides, a 2nd pole plate B of this capacitor C operationally connected to the control gate of one memory cell at least is connected through a 2nd switching means TB to a reference voltage source GND so that this capacitor can be charged at a positive high voltage. Next, the 1st pole plate of this capacitor is connected through the 1st switching means to the reference voltage source and the 2nd pole plate of this capacitor is disconnected from the reference voltage source so that a negative voltage can be provided on the 2nd pole plate.

    8.
    发明专利
    未知

    公开(公告)号：DE60318419D1

    公开(公告)日：2008-02-14

    申请号：DE60318419

    申请日：2003-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRAZZELLI DANIELA ,  BALDI LIVIO ,  SERVALLI GIORGIO

    IPC: H01L21/762

    Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

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