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公开(公告)号:ITUB20152221A1
公开(公告)日:2017-01-15
申请号:ITUB20152221
申请日:2015-07-15
Applicant: ST MICROELECTRONICS SRL , ST MICROELECTRONICS SRL
Inventor: NICOLLINI GERMANO , MODAFFARI ROBERTO , GARBARINO MARCO , GUANZIROLI FEDERICO
IPC: G01C19/5776 , H03H7/18
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公开(公告)号:IT1395939B1
公开(公告)日:2012-11-02
申请号:ITMI20091683
申请日:2009-09-30
Applicant: ST MICROELECTRONICS SRL
Inventor: GUANZIROLI FEDERICO , ZAMPROGNO MARCO , CONFALONIERI PIERANGELO
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公开(公告)号:ITMI20080183A1
公开(公告)日:2009-08-07
申请号:ITMI20080183
申请日:2008-02-06
Applicant: ST MICROELECTRONICS SRL
Inventor: GUANZIROLI FEDERICO , NICOLLINI GERMANO
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公开(公告)号:ITMI20091683A1
公开(公告)日:2011-04-01
申请号:ITMI20091683
申请日:2009-09-30
Applicant: ST MICROELECTRONICS SRL
Inventor: CONFALONIERI PIERANGELO , GUANZIROLI FEDERICO , ZAMPROGNO MARCO
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公开(公告)号:ITUB20155858A1
公开(公告)日:2017-05-24
申请号:ITUB20155858
申请日:2015-11-24
Applicant: ST MICROELECTRONICS SRL
Inventor: BIANCHI DARIO , GUANZIROLI FEDERICO , GHISU DAVIDE UGO
IPC: H03K3/356 , H03K19/0185
Abstract: In an embodiment, a level shifter circuit for driving a load (HSP) via a power supply line (HVP) includes: - an input stage (CL) for receiving an input signal (IN) switchable between a first and a second input level (0, LVP), - an output stage (LL, A) coupled to the power supply line (HVP) to produce a drive signal (G) for the load (HSP), the output stage (LL, A) switchable between a first and a second output level (REF_HVP, HVP), - a level translator (LT) set between the input stage (CL) and the output stage (LL, A), whereby the input signal (IN) switching between the first and second input levels (0, LVP) translates into the output stage (LL, A) switching between the first and second output levels (REF_HVP, HVP)- A feedback element (10) is provided coupled to the output stage (LL, A) for transferring to the input stage (CL) a feedback signal (20) representative of the output level of the output stage (LL, A); the input stage (CL) includes control circuitry (12 to 18, 22) sensitive to the input signal (IN) and the feedback signal (Q_N) for detecting undesired switching of the output stage (LL, A) between the first and second output levels (REF_HVP, HVP) occurring in the absence of input signal (IN) switching between the first and second input levels (0, LVP), the control circuitry (12 to 22) being configured (22) for inverting the output level (Q_N) of the output stage (LL, A) resulting from undesired switching.
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