中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

17 records (took 0.023 seconds)

    DIFFERENTIAL TO SINGLE-ENDED CONVERSION CIRCUIT AND COMPARATOR USING THE CIRCUIT
    1.
    发明申请
    DIFFERENTIAL TO SINGLE-ENDED CONVERSION CIRCUIT AND COMPARATOR USING THE CIRCUIT 审中-公开
    与使用电路的单端转换电路和比较器差分

    公开(公告)号：WO2008026228A8

    公开(公告)日：2008-07-03

    申请号：PCT/IT2006000629

    申请日：2006-08-28

    Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

    Inventor： ZAMPROGNO MARCO ,  CONFALONIERI PIERANGELO ,  MINUTI ALBERTO

    IPC: H03F3/00 ,  H03F3/45

    CPC classification number: H03F3/005 ,  H03F3/45192 ,  H03F2203/45028 ,  H03F2203/45138 ,  H03F2203/45396 ,  H03F2203/45534 ,  H03F2203/45726

    Abstract: An electrical circuit (1) for conversion from differential to single-ended is described, comprising: a differential amplifier stage (2) having a first (IN+) and a second (IN") input; a first (5) and a different second charging circuit (6) of the differential stage that can be operatively coupled, respectively, with an output (OUT*) of the conversion circuit (1) and with an auxiliary output (AUXOUT*). The circuit also comprises a first (7) and a second (8) buffer circuit each functionally arranged between one of said outputs\and between one of said charging circuits. The buffer circuits being configured so as to minimise a difference between the relative impedances seen towards said outputs (OUT*, AUXOUT*).

    Abstract translation: 一种用于从差分到单端转换的电路（1），包括：具有第一（IN +）和第二（IN“）输入的差分放大级（2）;第一（5）和不同的第二 分别与转换电路（1）的输出（OUT *）和辅助输出（AUXOUT *）可操作地耦合的差分级的充电电路（6），该电路还包括第一（7） 以及第二缓冲电路，每个功能地布置在所述输出之一和所述充电电路中的一个之间，缓冲电路被配置为最小化所述输出（OUT *，AUXOUT * ）。

    BUFFER DEVICE FOR SWITCHED CAPACITY CIRCUIT
    2.
    发明申请
    BUFFER DEVICE FOR SWITCHED CAPACITY CIRCUIT 审中-公开
    缓冲器装置的开关电容电路

    公开(公告)号：WO2008023395A8

    公开(公告)日：2008-07-03

    申请号：PCT/IT2006000628

    申请日：2006-08-25

    Applicant: ST MICROELECTRONICS SRL ,  ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

    Inventor： ZAMPROGNO MARCO ,  NICOLLINI GERMANO ,  MINUTI ALBERTO

    IPC: H03F3/00

    CPC classification number: H03F1/3211 ,  H03F3/005 ,  H03F3/45475 ,  H03F3/45977 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45212 ,  H03F2203/45514

    Abstract: An integrated buffer device (2) for a switched capacity circuit is described, comprising: - a buffer (7) having an output (OUT) for an output voltage dependent upon an input voltage (VIN) that can be supplied by a source (1) to the buffer device; - a capacitative switching component (C I ) that can be switched between a first and second condition in which it is connected, respectively, to the source and to the buffer to transfer the input voltage onto the output; said component being provided with a terminal (N2) having an associated stray capacity (C pi ). The device also comprises a charging and discharging device (SW CPIR , SW G ) configured to pre- charge the stray capacity at a reference voltage (REFM) before taking up the second condition and to pre-discharge the stray capacity before taking up the first condition.

    Abstract translation: 描述了一种用于开关电容电路的集成缓冲器件（2），包括： - 缓冲器（7），其具有用于依赖于输入电压（VIN）的输出电压的输出（OUT），该输出电压可以由源 ）到缓冲设备; - 可以在第一和第二条件之间切换的电容性开关元件（C I ），在所述第一和第二条件下，所述第一和第二条件分别连接到源极和缓冲器以将输入电压传输到输出端; 所述组件设置有具有相关寄生容量（C pi ）的终端（N2）。 该器件还包括一个充电和放电装置（SW CPIR ，SW G ），用于在占用第二个参考电压（REFM）前对杂散电容进行预充电 条件并在占用第一条件之前预先放电杂散容量。

    5.
    发明专利
    未知

    公开(公告)号：AT303674T

    公开(公告)日：2005-09-15

    申请号：AT02743185

    申请日：2002-06-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

    9.
    发明专利
    未知

    公开(公告)号：ITRM20010407A1

    公开(公告)日：2003-01-10

    申请号：ITRM20010407

    申请日：2001-07-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONFALONIERI PIERANGELO ,  ZAMPROGNO MARCO ,  NAGARI ANGELO

    IPC: H03M1/06 ,  H03M1/46 ,  H03M1/80

    Abstract: An A/D converter having capacitors of a first array of sampling capacitors weighted in binary code connected between a first common circuit node and an input terminal to be charged to an input voltage with respect to a ground of a signal to be converted, and in accordance with SAR technique are then selectively connected with two differential reference terminals, and at the same time capacitors of a second array equal to the first and all connected to a second node are selectively connected to ground and the lower differential voltage terminal. The two nodes are connected to the respective inputs of a comparator. A logic unit controls the connections of the capacitors of the two arrays in accordance with a predetermined timing program and as a function of the output of the comparator.

Patent Agency Ranking