7.
    发明专利
    未知

    公开(公告)号:IT1319597B1

    公开(公告)日:2003-10-20

    申请号:ITMI20002763

    申请日:2000-12-20

    Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

    8.
    发明专利
    未知

    公开(公告)号:DE69933670D1

    公开(公告)日:2006-11-30

    申请号:DE69933670

    申请日:1999-08-31

    Abstract: This invention relates to a CMOS technology temperature sensor of a type which comprises a first circuit portion (2) arranged to generate an electric voltage signal whose value increases with the temperature to be sensed, and a second circuit portion (3) arranged to generate an electric voltage signal whose value decreases with the temperature to be sensed. A comparator (4) is provided as an output stage for comparing the values of both voltage signals. Advantageously, the generator element of the second circuit portion (3) is a vertical bipolar transistor connected in a diode configuration.

    9.
    发明专利
    未知

    公开(公告)号:ITMI20002763A1

    公开(公告)日:2002-06-20

    申请号:ITMI20002763

    申请日:2000-12-20

    Abstract: A reading circuit is provided for reading a memory cell. The reading circuit includes a reference current source, a memory cell biased between its first and second terminals at a predetermined voltage, comparison means for comparing a current flowing in the memory cell with the reference current, and a control gate voltage source coupled to a third terminal of the memory cell. The control gate voltage source includes a virgin memory cell that is biased between two terminals with a voltage of equal value to the biasing voltage of the memory cell. The control gate voltage source produces a control gate voltage at another terminal of the virgin memory cell. In one preferred embodiment, the memory cell and the virgin memory cell are EEPROM cells.

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