公开(公告)号：JP2000195169A

公开(公告)日：2000-07-14

申请号：JP35109399

申请日：1999-12-10

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  MALFA MAURIZIO ,  BOLLATI GIACOMINO

IPC: G11B5/09 ,  G11B5/012 ,  G11B20/10

Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for pre-compensating interference between marks in a large capacity storage device. SOLUTION: This device supplys a digital data stream (I) and a clock signal (Ck) to be stored in a 1st circuit and also makes the 1st circuit(CC1) output a pair of digital streams (N, R). Further, the digital streams (N, R) and the clock signal (Ck) are supplied to a 2nd circuit (DC1), and the 2nd circuit outputs a digital data stream (O) directed to a write head. In such a case, by sampling the two digital streams (N, R) by a pair of flip-flops (FN2, FR2) and also re- coupling the signals outputted from the pair of flip-flops (FN1, FR2) with a digital data stream (O) via a logical XOR gate (X1), the device delays a transition immediately following a preceding transition by a predetermined time interval (Δwp).

公开(公告)号：DE69819919D1

公开(公告)日：2003-12-24

申请号：DE69819919

申请日：1998-12-15

Applicant: ST MICROELECTRONICS SRL

Inventor： DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  MALFA MAURIZIO ,  BOLLATI GIACOMINO

IPC: G11B5/09 ,  G11B5/012 ,  G11B20/10

Abstract: A method of delaying by a certain time interval ( DELTA wp) a transition in a digital data stream (O) fed to a write head of a mass storage device when said transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbolic nonlinear interference effects suffered when reading the stored data, comprises feeding to a first circuit (CC1) a digital data stream (I) to be stored and a clock signal (Ck) and outputting from said first circuit (CC1) a pair of digital streams (N, R), a first stream (N) assuming a first logic value every time a transition of said input stream occurs during a clock phase not successive to a clock phase during which a transition of said input stream (I) has occurred, the second stream (R) assuming said first logic value every time a transition of said input stream (I) occurs during a clock phase following a clock phase during which a transition has taken place in said input stream (I); feeding said two digital stream (N, R) and said clock signal (Ck) to as many inputs of a second circuit (DC1) and outputting from said second circuit said digital data stream (O) directed to the write head, in which the transitions immediately following a preceding transition are delayed by said pre-established time interval ( DELTA wp), by sampling the two digital streams (N, R) with a pair of flip-flops (FN2, FR2), each of which is respectively timed by clock signals respectively delayed by a certain different time interval ( DELTA n, DELTA r) and such that the difference between said different delay intervals is equal to said pre-established time interval ( DELTA n- DELTA r= DELTA wp) and recombining the signals output from said pair of flip-flops (FN2, FR2) through an logic XOR gate (X1) into said digital data stream (O).