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19 records (took 0.024 seconds)

    1.
    发明专利
    未知

    公开(公告)号：ITTO990291A1

    公开(公告)日：2000-10-13

    申请号：ITTO990291

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C7/12 ,  G11C16/28 ,  G11C16/32

    Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

    2.
    发明专利
    未知

    公开(公告)号：ITTO990290A1

    公开(公告)日：2000-10-13

    申请号：ITTO990290

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C16/28

    Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

    6.
    发明专利
    未知

    公开(公告)号：DE602004021599D1

    公开(公告)日：2009-07-30

    申请号：DE602004021599

    申请日：2004-09-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINES IGNAZIO ,  LA PLACA MICHELE

    IPC: G11C16/28

    Abstract: Described herein is a reading circuit (5) for a nonvolatile memory device (1), wherein the currents flowing through an array memory cell (12) to be read, and a reference memory cell (15) with known contents, are converted into an array voltage (V M ) and, respectively, into a reference voltage (V R ), which are compared to determine the contents of the array memory cell (12). The method envisages reducing the electrical stress to which the reference memory cell (15) is subjected during reading, by generating and holding a sample (V 2 ) of the reference voltage (V R ), then deselecting the reference memory cell (15), and then continuing reading using the sample (V 2 ) of the reference voltage (V R ).

    9.
    发明专利
    未知

    公开(公告)号：IT1307687B1

    公开(公告)日：2001-11-14

    申请号：ITTO990291

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C7/12 ,  G11C16/28 ,  G11C16/32

    Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

    10.
    发明专利
    未知

    公开(公告)号：DE602005016539D1

    公开(公告)日：2009-10-22

    申请号：DE602005016539

    申请日：2005-07-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: H03K17/16

    Abstract: A self-adaptive output buffer ( 130 ) for an output terminal of an electronic circuit ( 100 ) suitable to be connected to a load ( Cload ) is proposed. The self-adaptive output buffer includes means for sensing ( 205 ) an indication of the capacitance of the load and means for driving ( 210 ) the load according to the sensing, wherein the means for sensing ( 205 ) includes capacitive means ( C S1 ) with a preset capacitance, means ( P S1 , N S1 ) for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring ( 230 , 225 ) a measuring voltage at the capacitive means due to a charge sharing between the capacitive means ( C S1 ) and the load ( Cload ).

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