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22 records (took 0.023 seconds)

    2.
    发明专利
    未知

    公开(公告)号：ITTO990291A1

    公开(公告)日：2000-10-13

    申请号：ITTO990291

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C7/12 ,  G11C16/28 ,  G11C16/32

    Abstract: An equalization control circuit having an equalization signal generating stage having an enabling input receiving an address transition signal, a disabling input receiving a disabling signal, and an output generating an equalization control signal. An auxiliary line is supplied at one initial terminal (35a) with a biasing voltage correlated to the reading voltage supplied to the addressed array cell. An equalization filter is connected to the end terminal of the auxiliary line and generates the disabling signal when the voltage at the end terminal of the auxiliary line exceeds a preset threshold value.

    3.
    发明专利
    未知

    公开(公告)号：ITTO990290A1

    公开(公告)日：2000-10-13

    申请号：ITTO990290

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C16/28

    Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

    4.
    发明专利
    未知

    公开(公告)号：DE602005016539D1

    公开(公告)日：2009-10-22

    申请号：DE602005016539

    申请日：2005-07-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: H03K17/16

    Abstract: A self-adaptive output buffer ( 130 ) for an output terminal of an electronic circuit ( 100 ) suitable to be connected to a load ( Cload ) is proposed. The self-adaptive output buffer includes means for sensing ( 205 ) an indication of the capacitance of the load and means for driving ( 210 ) the load according to the sensing, wherein the means for sensing ( 205 ) includes capacitive means ( C S1 ) with a preset capacitance, means ( P S1 , N S1 ) for charging the capacitive means to a preset voltage, means for coupling the charged capacitive means with the load, and means for measuring ( 230 , 225 ) a measuring voltage at the capacitive means due to a charge sharing between the capacitive means ( C S1 ) and the load ( Cload ).

    5.
    发明专利
    未知

    公开(公告)号：DE602004004597T2

    公开(公告)日：2007-11-15

    申请号：DE602004004597

    申请日：2004-10-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PISASALE MICHELANGELO ,  GAIBOTTI MAURIZIO ,  LA PLACA MICHELE

    IPC: G11C5/14 ,  G11C16/30

    Abstract: A voltage-down converter ( 125 ) for providing an output voltage (Vo) lower than a power supply voltage (Vdd) of the converter is proposed. The converter includes voltage regulation means ( 205 ) for obtaining an intermediate voltage (Vr) corresponding to the output voltage from the power supply voltage by controlling a variable-conductivity element ( Tr ) with a control signal (Vg) resulting from a comparison between the intermediate voltage (Vr) and a reference voltage (Vbg), and an output stage ( 220,225 1 - 225 N ) for obtaining the output voltage from the power supply voltage by controlling a further variable-conductivity element ( Tsb,T 1 - T N ) with the control signal, wherein the further variable-conductivity element has a modular structure with at least one set ( MM,ML,MH ) of multiple basic modules ( 225 1 - 225 N ), the converter further including means ( 230,SW 1 - SW N ) for enabling and/or disabling the modules of each set in succession according to a comparison between the output voltage and the intermediate voltage.

    8.
    发明专利
    未知

    公开(公告)号：IT1307686B1

    公开(公告)日：2001-11-14

    申请号：ITTO990290

    申请日：1999-04-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CONDEMI CARMELO ,  LA PLACA MICHELE ,  MARTINES IGNAZIO

    IPC: G11C16/28

    Abstract: A reading circuit for nonvolatile memory cells, including a current-to-voltage converter, having an array load, connected to a memory cell, and a reference load connected to a reference generator. The array load and the reference load include PMOS transistors presenting an array shape factor (W/L)F and, respectively, a reference shape factor (W/L)R. The reading circuit further includes a charge pump that supplies a biasing voltage to a gate terminal of the memory cell. The biasing voltage is proportional to and higher than a supply voltage VDD. The ratio between the array shape factor (W/L)F and the reference shape factor (W/L)R is a non-integer.

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