公开(公告)号：ITVA20020067A1

公开(公告)日：2004-06-05

申请号：ITVA20020067

申请日：2002-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： BELLINI ANDREA ,  DEFENDI MARCO ,  MAGNAVACCA ALESSANDRO ,  MASTROIANNI FRANCESCO

IPC: G06K20060101 ,  G11C7/10 ,  G11C8/12

公开(公告)号：ITMI20050838A1

公开(公告)日：2006-11-12

申请号：ITMI20050838

申请日：2005-05-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CUSSOTTO ELENA ,  MASTROIANNI FRANCESCO ,  MOLLICHELLI MASSIMILIANO ,  MONDELLO ANTONINO ,  SALI MAURO

公开(公告)号：ITVA20020067D0

公开(公告)日：2002-12-04

申请号：ITVA20020067

申请日：2002-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： MAGNAVACCA ALESSANDRO ,  BELLINI ANDREA ,  MASTROIANNI FRANCESCO ,  DEFENDI MARCO

IPC: G11C7/10 ,  G11C8/12

Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2 n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.