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    LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY
    1.
    发明专利
    LAYOUT OF REDUNDANCY CIRCUIT FOR SEMICONDUCTOR MEMORY 失效

    公开(公告)号：JPH08102527A

    公开(公告)日：1996-04-16

    申请号：JP6925895

    申请日：1995-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  CARRERA MARCELLO ,  DEFENDI MARCO

    IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10

    Abstract: PURPOSE: To provide the layout of a redundancy circuit, wherein the chip area required for realization of redundancy becomes a minimum area. CONSTITUTION: An array MAR of a programmable nonvolatile memory, which stores a redundancy bit line, a redundancy word line, a defective bit line, which should be functionally replaced respectively, and the address of a word line is provided. The layout of the redundancy circuit is divided into a plurality of the same layout strips LS1-LS4, which intersect the array at right angles and have first and second strip parts at both sides of the array. The first strip part intersects a column-address signal bus CABUS, extending in parallel with the array. The second strip part intersects a row-address signal bus (RABUS), extending in parallel with the array.

    4.
    发明专利
    未知

    公开(公告)号：DE69516883T2

    公开(公告)日：2000-10-05

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    5.
    发明专利
    未知

    公开(公告)号：DE69516883D1

    公开(公告)日：2000-06-15

    申请号：DE69516883

    申请日：1995-12-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VILLA CORRADO ,  DEFENDI MARCO ,  BETTINI LUIGI

    IPC: G11C16/16 ,  G11C11/00

    Abstract: The invention relates to a method of erasing an electrically programmable non-volatile memory device constructed as a multi-sector matrix memory and being of the type with an erase algorithm integrated into the device. The method comprises the following steps: erasing some or all of the matrix sectors in parallel; subsequently reading and checking each erased sector; storing the address of a sector being checked when the issue of a check is unfavorable; carrying out a fresh parallel erasing step; and starting a new reading/checking step from the sector that has checked unfavorably.

    6.
    发明专利
    未知

    公开(公告)号：ITVA20020067D0

    公开(公告)日：2002-12-04

    申请号：ITVA20020067

    申请日：2002-12-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGNAVACCA ALESSANDRO ,  BELLINI ANDREA ,  MASTROIANNI FRANCESCO ,  DEFENDI MARCO

    IPC: G11C7/10 ,  G11C8/12

    Abstract: The memory device includes a plurality of memory chips of a certain capacity assembled in a single package and sharing input/output pins, the memories being selectable and singularly enabled one at the time by appropriate external commands coherently with the currently addressed memory location. The device uses only one external enable/disable logic command applied through a single dedicated pin. Each of the memory chips has a number of additional input/output pads equal to 2*n, where 2 n is the number of memory chips contained in the device, and a dedicated circuit that generates an internal enable/disable command, as a function of logic inputs corresponding to the logic states of the additional pads and the external enable/disable command.

    7.
    发明专利
    未知

    公开(公告)号：DE69412234D1

    公开(公告)日：1998-09-10

    申请号：DE69412234

    申请日：1994-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  CARRERA MARCELLO ,  DEFENDI MARCO

    IPC: G11C17/00 ,  G11C5/02 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/822 ,  H01L27/04 ,  H01L27/10 ,  G06F11/20

    Abstract: A Redundancy circuitry layout for a semiconductor memory device comprises an array (MAR) of programmable non-volatile memory elements (TF0,TF1) for storing the addresses of defective bit lines and word lines which must be functionally replaced respectively by redundancy bit lines and word lines; the redundancy circuitry layout is divided in identical layout strips (LS1-LS4) which are perpendicular to the array (MAR) of memory elements (TF0,TF1) and which comprise each a first and a second strip sides located at opposite sides of the array (MAR) of memory elements (TF0,TF1), the first strip side containing at least one programmable non-volatile memory register (CRRA,CRRB) of a first plurality for the selection of redundancy bit lines and being crossed by a column address signal bus (CABUS) running parallel to the array (MAR of memory elements (TF0,TF1), the second strip side containing one programmable non-volatile memory register (RRR) of a second plurality for the selection of redundancy word lines and being crossed by a row address signal bus (RABUS) running parallel to the array (MAR) of memory elements (TF0,TF1).

    8.
    发明专利
    未知

    公开(公告)号：DE69531349D1

    公开(公告)日：2003-08-28

    申请号：DE69531349

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  DELLABORA MARCO ,  DEFENDI MARCO

    IPC: G11C16/12 ,  G11C16/30 ,  H02M3/07 ,  H03K3/03 ,  G11C16/06

    Abstract: The present invention relates to a clock generator circuit (7) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2). In particular, the clock generator circuit according to the invention comprises a loop (14) of a plurality of primary inverters (15) and secondary inverters (16) supplying clock signals (ck ,ck ,ck ,ck ) on a plurality of outputs (07), each of the primary inverters (15) having an input terminal (I15) connected to an output terminal (016) of a secondary inverter (16) preceding it in the loop (14), and to the ground voltage reference (GND) through a MOS transistor (N1) controlled by a secondary control signal (PROGN) which corresponds to the negated control signal (PROG), in parallel with a capacitor (C), and having an output terminal (015) connected to a first input (A) of the secondary inverter (16) lying next to it in the loop (14), and to one of the output terminals (07) The invention also concerns a charge pump circuit and a phase generator (9) for a programming circuit of a matrix array of electrically programmable non-volatile memory cells (2) as well as to a three-terminal capacitor.

    10.
    发明专利
    未知

    公开(公告)号：DE69515669T2

    公开(公告)日：2000-07-27

    申请号：DE69515669

    申请日：1995-10-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  DALLABORA MARCO ,  DEFENDI MARCO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises: a plurality of charge pump stages (S1-S6), each charge pump stage (S1-S6) having an input node (I1-I6) and an output node (O1-O6) and comprising a pass transistor (P11-P16) and a first couplig capacitor (C21-C26), the pass transistor (P11-P16) having a first terminal connected to the input node (I1-I6), a second terminal connected to the output node (O1-O6) and a control terminal connected to an internal node (1-6) of the charge pump stage (S1-S6), said first coupling capacitor (C21-C26) having a first plate connected to said output node (O1-O6) and a second plate connected to a respective clock signal (A,B,C,D); negative voltage regulation means (7) for regulating a negative output voltage (V(O)) on an output node (O) of the negative charge pump circuit to provide a fixed negative voltage value. The negative charge pump circuit comprises at least one negative voltage limiting means (P7) electrically coupling said output node (O) of the negative charge pump circuit with the internal node (6) of the last charge pump stage (S6) of the negative charge pump circuit to limit the negative voltage on said internal node (6) and on the output node (O6) of said last charge pump stage (S6).

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