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7 records (took 0.022 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE102007051192A1

    公开(公告)日：2008-06-05

    申请号：DE102007051192

    申请日：2007-10-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MAGNAVACCA ALESSANDRO ,  SCOTTI MASSIMILIANO ,  DEL GATTO NICOLA ,  NAVA CLAUDIO ,  FERRARIO MARCO ,  MOLLICHELLI MASSIMILIANO

    IPC: G11C16/06

    Abstract: A memory device may include an array of addressable three-level cells, a coding circuit being input with three-bit strings and generating corresponding ternary strings based upon a code, and a program circuit being input with the ternary strings and storing them in respective pairs of three-level cells. The memory device also may include a read circuit reading stored ternary strings in the respective pairs of three-level cells, and a decoding circuit being input with the stored ternary strings and generating corresponding strings of three bits based upon the code.

    2.
    发明专利
    未知

    公开(公告)号：DE602004012271T2

    公开(公告)日：2009-03-19

    申请号：DE602004012271

    申请日：2004-10-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

    IPC: G11C16/24

    Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

    3.
    发明专利
    未知

    公开(公告)号：DE602004012271D1

    公开(公告)日：2008-04-17

    申请号：DE602004012271

    申请日：2004-10-08

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SFORZIN MARCO ,  DEL GATTO NICOLA ,  MOLLICHELLI MASSIMILIANO ,  SCOTTI MASSIMILIANO

    IPC: G11C16/24

    Abstract: In a memory device (1; 30) having an array (2) of memory cells (3), a column decoder (9) is configured to address the memory cells (3), and a charge-pump supply circuit (6; 32) generates a boosted supply voltage (V b ; V yr ) for the column decoder (9). A connecting stage (22) is arranged between the supply circuit (6; 32) and the column decoder (9); the connecting stage (22) switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device (1; 30), in particular during a reading step.

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