公开(公告)号：DE69927927D1

公开(公告)日：2005-12-01

申请号：DE69927927

申请日：1999-12-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PASETTI MAURO ,  MILANESE CARLO MARIA

IPC: H04M3/00 ,  H04M11/06 ,  H04M19/00

公开(公告)号：DE69628833D1

公开(公告)日：2003-07-31

申请号：DE69628833

申请日：1996-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MILANESE CARLO MARIA ,  PASETTI MAURO

IPC: H04M15/00 ,  H04M15/28 ,  H04Q3/42

Abstract: The present invention relates to a control signal generation circuit for telephone charge indicators comprising a capacitor (CS) having a first (C+) and a second (C-) terminals connected to ground (GND) through respectively a first (S1) and a second (S2) switches with the first terminal (C+) of the capacitor (CS) being also connected through a third switch (S3) to a constant current generator (I0) which is connected to a positive power supply line with respect to ground (Vdd). The second terminal (C-) of the capacitor (CS) is connected to a constant current generator (I0) which is connected to a negative power supply line with respect to ground (Vss). The first and second terminals are also connected through respectively a first (RS1) and a second (RS2) resistance to a circuit node coupled to an output terminal (OUT).

公开(公告)号：ITVA990005A1

公开(公告)日：2000-08-22

申请号：ITVA990005

申请日：1999-02-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MILANESE CARLO MARIA ,  CASTELLO RINALDO

IPC: H03K3/3565 ,  H03K5/24

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

公开(公告)号：DE60025584D1

公开(公告)日：2006-04-06

申请号：DE60025584

申请日：2000-05-12

Applicant: ST MICROELECTRONICS SRL

Inventor： GUINEA JESUS ,  TOMASINI LUCIANO ,  MILANESE CARLO MARIA

IPC: H04B3/14 ,  H03H11/04

Abstract: The present invention refers to a method and to an equalizer circuit of signals transmitted on a line. In an embodiment the equaliser circuit of signals transmitted on a line having an attenuation comprising: an analogical adaptive filter (1) applied in series to said line comprises at least two transconductance filters having a bias current (Pc1-Pcn) each and to which it is associated at least one pole and at least one zero the position in frequency of which in the working band (B) is variable in response to said bias current (Pc1-Pcn); a retroaction circuit (3, 4, 5, 6, 7) applied to the output of said filter (1) able to vary said bias current (Pc1-Pcn); said bias current (Pc1-Pcn) varies at the varying of said attenuation of said line; characterised in that said at least two transconductance filters have said bias current of prefixed value; said bias current is made to vary at the increasing of said attenuation so that said at least one pole is moved toward the high frequencies; said bias current is made to vary at the increasing of said attenuation so that said at least a zero is moved toward the low frequencies.

公开(公告)号：ITVA990005D0

公开(公告)日：1999-02-22

申请号：ITVA990005

申请日：1999-02-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MILANESE CARLO MARIA ,  CASTELLO RINALDO

IPC: H03K3/3565 ,  H03K5/24

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.

公开(公告)号：IT1313381B1

公开(公告)日：2002-07-23

申请号：ITVA990005

申请日：1999-02-22

Applicant: ST MICROELECTRONICS SRL

Inventor： MILANESE CARLO MARIA ,  CASTELLO RINALDO

IPC: H03K3/3565 ,  H03K5/24

Abstract: A comparator circuit includes a differential input stage, a second differential stage having a differential output, and an output stage transforming an output signal from the differential output of the second differential stage into an output signal having a logic level. The comparator further includes a common mode measuring stage. The common mode measuring stage includes a differential pair of input transistors and a differential pair of complementary transistors biased by respective current generators, and a current mirror summing the differential output currents of the two complementary transistors pairs into a single output current signal. A switching stage is controlled by the differential output nodes of the second differential stage. A common source node of the switch stage is coupled to the output of the common mode measuring stage and to the differential output nodes of the differential input stage.