公开(公告)号：DE69431598D1

公开(公告)日：2002-11-28

申请号：DE69431598

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FREDERICO ,  VAJANA BRUNO ,  PARUZZI PAOLA

IPC: G11C17/00 ,  G05F3/24 ,  G11C5/14 ,  G11C11/56 ,  G11C16/06

Abstract: The present invention relates to a monolithically integrable predetermined voltage generator (1) comprising a node (IN) held at a constant voltage (Vpp) and a plurality of circuit branches (2a, 2b, 2c and 2d) each of which incorporates at least one turn on control terminal (3a, 3b, 3c and 3d) and which are interconnected in such a manner that at least one of them leads to said node (IN). Across each of the branches (2a, 2b, 2c and 2d) a corresponding voltage drop is present when the branch is turned on and obtained from a certain number of active elements included in the branch. In accordance with a preferred embodiment, diode-connected MOS transistors are used as active elements. The generator also comprises an output terminal (OUT) associated with at least one of said branches at which is generated a predetermined voltage value. A control signal is applied to at least one turn on control terminal (3a, 3b, 3c and 3d) of said plurality of branches for turning on a predetermined subset of said plurality of branches and generating at the output terminal (OUT) a voltage lower than that at said node (IN). Each of the predetermined voltage values is a predetermined combination of the voltage drops on the turned on branches. In a preferred application, the generator of the present invention is used in a multilevel EEPROM memory circuit for generating a plurality of programming voltages for the memory cells.

公开(公告)号：DE69528816D1

公开(公告)日：2002-12-19

申请号：DE69528816

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PARUZZI PAOLA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

公开(公告)号：DE69528816T2

公开(公告)日：2003-10-23

申请号：DE69528816

申请日：1995-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： PIO FEDERICO ,  PARUZZI PAOLA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/00

公开(公告)号：DE69523287D1

公开(公告)日：2001-11-22

申请号：DE69523287

申请日：1995-03-03

Applicant: ST MICROELECTRONICS SRL

Inventor： BALDI LIVIO ,  PARUZZI PAOLA

IPC: H01L27/115 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: The present invention concerns an electrically programmable and erasable non-volatile memory cell having a traditional structure but being inverted in the conductivity type of the component elements and missing from the second source diffusion. In addition to possessing the known advantages of p-channel EPROM cells such as low consumption and which are still more important in view of the typical applications of FLASH and EEPROM memories they are easier to integrate with MOS transistors of traditional logic circuits because their structure is more similar thereto.