公开(公告)号：DE69528967D1

公开(公告)日：2003-01-09

申请号：DE69528967

申请日：1995-05-31

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUCCOLTRI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

IPC: G05F3/22 ,  G05F3/26 ,  H03F3/343 ,  H03K17/04 ,  H03K17/60 ,  G05F1/00

公开(公告)号：DE69520562T2

公开(公告)日：2001-07-12

申请号：DE69520562

申请日：1995-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

公开(公告)号：DE69520562D1

公开(公告)日：2001-05-10

申请号：DE69520562

申请日：1995-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

公开(公告)号：DE69515869T2

公开(公告)日：2000-12-07

申请号：DE69515869

申请日：1995-09-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

公开(公告)号：DE69515869D1

公开(公告)日：2000-04-27

申请号：DE69515869

申请日：1995-09-14

Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

公开(公告)号：DE69625192D1

公开(公告)日：2003-01-16

申请号：DE69625192

申请日：1996-08-07

Applicant: ST MICROELECTRONICS SRL

Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  DEMICHELI DAVIDE ,  PATTI GIUSEPPE

IPC: G11B5/55 ,  G11B5/596 ,  G11B21/10 ,  G11B5/00

Abstract: A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the centre of a recorded track, comprising a peak detector (5) for successively and individually sampling the amplitude of each of a plurality of peaks of the said pair of alternating signals, and a capacitor (9) periodically connected to the output of the peak detector (5) by a control logic (7) for deriving a weighted average of the various successively sampled amplitudes, obtaining an averaged measure of amplitude with high immunity to noise.