公开(公告)号：JPH10341588A

公开(公告)日：1998-12-22

申请号：JP11661198

申请日：1998-04-27

Applicant: ST MICROELECTRONICS SRL

Inventor： POZZONI MASSIMO ,  PEDRAZZINI GIORGIO

IPC: H02P6/16 ,  G05F20060101 ,  H02P6/06 ,  H02P6/08 ,  H02P6/182

Abstract: PROBLEM TO BE SOLVED: To detect the zerocross of the current of an inductive load without monitoring the current of an exclusive detective resistor in series with inductive load. SOLUTION: To detect the zero-cross of the current of the inductive load Ls driven in voltage mode through the half bridge consisting of a switch on high order side and a switch on low order side driven in opposite phases to each other by PWM signals, the voltage value at the output node A of the half bridge is compared with a fixed reference voltage value Vref, and the direction of the current in the inductive load Ls is judged from the comparison result. The comparison results are sampled cyclically during the period when both the switches mentioned above are off. Then, the zero cross can be detected by the inversion of the comparative value between the two continuous samplings.

公开(公告)号：AT557472T

公开(公告)日：2012-05-15

申请号：AT10179881

申请日：2010-09-27

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  POZZONI MASSIMO

IPC: H03H11/04

Abstract: An architecture of an integrator has an input transconductance amplifier Gi having an output resistance adjustable independently from the transconductance gain Gi, through a dedicated control signal, and includes also a matched transconductance amplifier Gi2 having an adjustable gain and an output resistance matched with that of the first transconductance amplifier Gi and adjusted by the same dedicated control signal. A reference current is forced through the matched output resistance and the dedicated control signal is generated such to keep constant the output voltage of the matched transconductance amplifier. A method of stabilization against PVT variations of the integrated circuit of an integrator is also disclosed.

公开(公告)号：DE69624493T2

公开(公告)日：2003-06-26

申请号：DE69624493

申请日：1996-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO MARIA ,  POZZONI MASSIMO ,  PEDRAZZINI GIORGIO ,  RICOTTI GIULIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

公开(公告)号：DE69624493D1

公开(公告)日：2002-11-28

申请号：DE69624493

申请日：1996-12-09

Applicant: ST MICROELECTRONICS SRL

Inventor： RAVANELLI ENRICO MARIA ,  POZZONI MASSIMO ,  PEDRAZZINI GIORGIO ,  RICOTTI GIULIO

IPC: H01L27/04 ,  H01L21/822 ,  H01L27/02 ,  H01L27/088

Abstract: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.