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    1.
    发明专利
    未知

    公开(公告)号：DE602006008480D1

    公开(公告)日：2009-09-24

    申请号：DE602006008480

    申请日：2006-09-13

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  RAVASIO ROBERTO ,  MARELLI ALESSIA

    IPC: G06F11/10 ,  G06F11/20

    Abstract: Basic redundancy information is non volatily stored in a reserved area (that is an area of the array that is not addressable by the user of the device) of the addressable area of the array and is copied on volatile storage supports at every power-on of the memory device. The unpredictable though statistically inevitable presence of fail array elements also in such a reserved area of the memory array that would corrupt the basic redundancy information as established during the test-on wafer (EWS) phase of the fabrication process and thus increasing the number of rejects, lowering the yield of the fabrication process, is effectively overcome by writing the basic redundancy data in the reserved area of the array with an ECC technique, using a certain error correction code that may be chosen among so-called majority codes 3, 5, 7, 15 and the like or Hamming code for 1, 2, 3 or more errors, in function of the fail probability of a memory cell as determined by the testing on wafer of the devices during fabrication (fail probability of the specific fabrication process used). A significant area saving is achieved compared to the use of fuse arrays and other known approaches.

    6.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    9.
    发明专利
    未知

    公开(公告)号：DE602005012625D1

    公开(公告)日：2009-03-19

    申请号：DE602005012625

    申请日：2005-07-22

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： BOVINO ANGELO ,  ALTIERI VINCENZO ,  RAVASIO ROBERTO ,  MICHELONI RINO ,  DE MATTEIS MARIO

    IPC: G11C11/56

    Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

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