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    1.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    2.
    发明专利
    未知

    公开(公告)号：DE602005012682D1

    公开(公告)日：2009-03-26

    申请号：DE602005012682

    申请日：2005-07-22

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： CRIPPA LUCA ,  MISSIROLI CHIARA ,  MICHELONI RINO

    IPC: G11C16/26 ,  G11C16/04

    Abstract: A reading method of a NAND memory device including the steps of: first connecting a first end terminal (12a) of a stack (12) of cells (3, 3', 3") to a reference line (13); second connecting a second end terminal (12b) of the stack (12) of cells (3, 3', 3") to a respective bitline (10); charging the bitline (10) to a predetermined bitline read voltage (V DR ), wherein one of the steps of first connecting and second connecting is carried out before charging the bitline (10) and the other of the steps of first connecting and second connecting is carried out after charging the bitline (10). An order of carrying out the steps of first connecting and second connecting is determined based on an address (MSB; AL2) of a selected cell (3', 3") .

    7.
    发明专利
    未知

    公开(公告)号：DE602005008396D1

    公开(公告)日：2008-09-04

    申请号：DE602005008396

    申请日：2005-05-20

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： RAGONE GIANCARLO ,  CRIPPA LUCA ,  SANGALLI MIRIAM ,  MICHELONI RINO

    IPC: G11C8/08 ,  G11C16/08 ,  H02M3/07 ,  H03K17/06

    Abstract: A high-voltage switch (24) has a high-voltage input terminal (29), receiving a high voltage (HV), and an output terminal (31). A pass transistor (36), having a control terminal, is connected between the high-voltage input terminal (29) and the output terminal (31). The output of a voltage-multiplying circuit (40) of the charge-pump type is connected to the control terminal. The voltage-multiplying circuit (40) is of a symmetrical type, has first and second charge-storage means (41, 42), receiving a clock signal (CK) of a periodic type, and has a first circuit branch (44, 48) and a second circuit branch (45, 49), which are symmetrical to one another and operate in phase opposition with respect to the clock signal (CK).

    READ CIRCUIT FOR NONVOLATILE MEMORY
    9.
    发明专利
    READ CIRCUIT FOR NONVOLATILE MEMORY 失效

    公开(公告)号：JP2001084782A

    公开(公告)日：2001-03-30

    申请号：JP2000253119

    申请日：2000-07-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  CAMPARDO GIOVANNI ,  CRIPPA LUCA

    IPC: G11C16/06 ,  G11C16/28

    Abstract: PROBLEM TO BE SOLVED: To eliminate the drawback that reduction of read time is limited at a low supply voltage. SOLUTION: A read circuit 1' comprises an array branch 6 having an input array node 22 connected, via an array bit line 8, to an array cell 10; a reference branch 12 having an input reference node 32 connected, via a reference bit line 14, to a reference cell 16; a current-to-voltage converter 18 connected to an output array node 56 of the array branch and to an output reference node of the reference branch to supply on both nodes 56, 58 the respective electric potentials VM, VR correlated to the currents flowing in both cells 10, 16; and a comparator 19 connected at input to both nodes 56, 58 and supplying as output a signal OUT indicative of the contents stored in the array memory cell 10; and an array decoupling stage 80 arranged between both array nodes 22, 56 to decouple both array nodes 22, 56 from one another.

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