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公开(公告)号：JPH04273537A
公开(公告)日：1992-09-29
申请号：JP27297291
申请日：1991-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: PURPOSE: To obtain a finite state machine that is used for a highly reliable computing/adjustment system. CONSTITUTION: A combination logic 10 connected to a state memory 11 via the connections which transmit a future state signal 12 and a present state signal 13 is included. The logic 10 includes an input terminal 14 for the external input signals of a finite state machine and also an output terminal 15 for the output signals produced by the logic 10 itself. The finite state machine includes a comparison means 17 which compares at least one reference level 16 with the signal 12. Then the means 17 sets an error signal 18 to a means that resets the finite state machine and/or an adjustment system.
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公开(公告)号：JPH03220913A
公开(公告)日：1991-09-30
申请号：JP30281290
申请日：1990-11-09
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233
Abstract: PURPOSE: To reduce dependency against the inclination of the input signal waveform of an output change by providing a second differential cell having one input connected to output and the other input connected to a control circuit part provided with respective outputs connected to threshold input. CONSTITUTION: A transistor T9 is provided with a base B9 which is directly connected to an output terminal OUT as input for a second differential cell 9 and a collector C9 connected to a power electrode Vc. In the other transistor T10, the base B10 is connected to ground via a current power as second input and is connected to the emitter E11 of an npn-type transistor T14. T14 is connected to become diode constitution in the device 1, and the collector C14 is directly connected to the emitter E15 of the transistor T15. Threshold input S is connected to the collector C10 of the transistor T10 in the cell 9 and a comparator 1 is provided with the circuit part 10 effective for controlling a voltage value Vs appearing on threshold input S. Thus, dependency against the inclination of the input signal waveform of the output change can be reduced.
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公开(公告)号：EP0427016B1
公开(公告)日：1997-12-29
申请号：EP90119873
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/2897 , H03K3/0233 , H03K3/023
CPC classification number: H03K3/02337
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公开(公告)号：IT1246467B
公开(公告)日：1994-11-19
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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Patent Agency Ranking
公开(公告)号：DE69129727D1
公开(公告)日：1998-08-13
申请号：DE69129727
申请日：1991-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
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公开(公告)号：IT1236692B
公开(公告)日：1993-03-26
申请号：IT2233589
申请日：1989-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03F
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：DE69031863D1
公开(公告)日：1998-02-05
申请号：DE69031863
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03K3/023
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：DE69031863T2
公开(公告)日：1998-04-16
申请号：DE69031863
申请日：1990-10-17
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCHI FABRIZIO , LIETAR LOIC , VAI GIANFRANCO , BETTI GIORGIO
IPC: H03K3/0233 , H03K3/2897 , H03K3/023
Abstract: An electronic comparator device (1) with hysteresis, being of a type which comprises a differential cell (2) having a signal input (IN), an output (OUT), and a threshold input (S), further comprises a second differential cell (9) having one input (B9) connected to said output (OUT) and the other input (B10) connected to a controlling circuit portion (10) which has an output (E11) connected to the threshold input (S) to reduce the threshold voltage value (Vs) stepwise on the first change-over of the output (OUT) of the comparator (1).
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公开(公告)号：IT9021816D0
公开(公告)日：1990-10-22
申请号：IT2181690
申请日：1990-10-22
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , ZUFFADA MAURIZIO , VAI GIANFRANCO , SACCHI FABRIZIO
Abstract: Finite-state machine for reliable computing and adjustment systems, which comprises a combinatorial logic (10) connected to a status memory (11) by means of connections which carry future state signals (12) and of connections which carry current state signals (13). The combinatorial logic (10) comprises input terminals (14) for input signals which are external to the finite-state machine and output terminals (15) for output signals generated by the combinatorial logic (10). The finite-state machine furthermore comprises means for comparing the future state signals (12) to at least one reference level (16); the comparison means set an error signal (18) toward means for resetting the finite-state machine and/or the system which includes it.
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