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公开(公告)号：DE69516402D1
公开(公告)日：2000-05-25
申请号：DE69516402
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
IPC: G11C11/56
Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.
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公开(公告)号：DE69514783D1
公开(公告)日：2000-03-02
申请号：DE69514783
申请日：1995-03-23
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).
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Patent Agency Ranking
公开(公告)号：DE69516402T2
公开(公告)日：2000-11-02
申请号：DE69516402
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
IPC: G11C11/56
Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.
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公开(公告)号：DE69514783T2
公开(公告)日：2000-06-08
申请号：DE69514783
申请日：1995-03-23
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).
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公开(公告)号：DE69626804D1
公开(公告)日：2003-04-24
申请号：DE69626804
申请日：1996-06-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT).
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公开(公告)号：DE69626804T2
公开(公告)日：2004-03-04
申请号：DE69626804
申请日：1996-06-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT).
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公开(公告)号：DE69526336D1
公开(公告)日：2002-05-16
申请号：DE69526336
申请日：1995-04-28
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , GASTALDI ROBERTO , TELECCO NICOLA , TORELLI GUIDO
IPC: G11C11/419 , G11C7/06 , G11C11/00
Abstract: A reading device for devices with memory cells with two branches each comprising, connected in cascade, an electronic switch (T3, T4), an active element (T1, T2) reactively connected to the active element of the other branch, between them to form a voltage amplifier. Each active element is controlled by means of a high impedance circuit element (DL, DR). A microswitch (TE) which connects the two branches together is inserted between the two active elements (1, 2).
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