公开(公告)号：DE60326351D1

公开(公告)日：2009-04-09

申请号：DE60326351

申请日：2003-10-22

Applicant: ST MICROELECTRONICS SRL

Inventor： CAMERLENGHI EMILIO ,  MAURELLI ALFONSO ,  PESCHIAROLI DANIELA ,  ZABBERONI PAOLA

IPC: H01L21/8247 ,  H01L21/8234 ,  H01L23/31 ,  H01L27/105

Abstract: A sealing method for electronic devices such as flash memory cells (4) and CMOS transistors (5) formed on a common semiconductor substrate (1) comprising the steps of:forming at least a first conductive layer (7,9) on a first portion of semiconductor substrate (1),forming a second conductive layer (11) on a second portion of semiconductor substrate (1),defining a first plurality of gate regions (4a) of the memory cells (4) in at least a first conductive layer (7),forming a first sealing layer (14) on the whole semiconductor substrate (1) to seal the first plurality of gate regions (4a),defining a second plurality of gate regions (5a) of the CMOS transistors (5) in the second conductive layer (11),forming a second sealing layer (16) on the whole semiconductor substrate (1) to seal the second plurality of gate regions (5a).