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    1.
    发明专利
    未知

    公开(公告)号：DE60323202D1

    公开(公告)日：2008-10-09

    申请号：DE60323202

    申请日：2003-02-21

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： KHOURI OSAMA ,  RESTA CLAUDIO

    IPC: G11C11/34 ,  G11C13/00 ,  G11C11/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/28 ,  G11C16/30

    Abstract: A phase change memory (20) has an array (1) formed by a plurality of cells (2), each including a memory element (3) of calcogenic material and a selection element (4) connected in series to the memory element; a plurality of address lines (11) connected to the cells; a write stage (24) and a reading stage (25) connected to the array. The write stage (24) is formed by current generators (45), which supply preset currents to the selected cells (2) so as to modify the resistance of the memory element (3). Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

    2.
    发明专利
    未知

    公开(公告)号：DE60227534D1

    公开(公告)日：2008-08-21

    申请号：DE60227534

    申请日：2002-11-18

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： KHOURI OSAMA ,  BEDESCHI FERDINANDO ,  RESTA CLAUDIO

    IPC: G11C11/34 ,  G11C7/04 ,  G11C16/02

    Abstract: A phase change memory includes a temperature sensor having a resistance variable with temperature with the same law as a phase-change storage element. The temperature sensor is formed by a resistor (20) of chalcogenic material furnishing an electrical quantity (V(T), I(T)) that reproduces the relationship between the resistance of a phase change memory cell and temperature; the electrical quantity is processed (21) so as to generate reference quantities as necessary for writing and reading the memory cells. The chalcogenic resistor (20) has the same structure as a memory cell and is programmed with precision, preferably in the reset state.

    Method and device for irreversibly programming and reading nonvolatile memory cell
    4.
    发明专利
    Method and device for irreversibly programming and reading nonvolatile memory cell 有权
    用于不可逆编程和读取非易失性存储器单元的方法和装置

    公开(公告)号：JP2009093786A

    公开(公告)日：2009-04-30

    申请号：JP2008280494

    申请日：2008-10-03

    Applicant: St Microelectronics Srl ,  エッセティマイクロエレクトロニクス ソシエタ ア レスポンサビリタ リミタータ

    Inventor： RESTA CLAUDIO ,  BEDESCHI FERDINANDO ,  PELLIZZER FABIO

    IPC: G11C13/00

    CPC classification number: G11C13/0069 ,  G11C11/005 ,  G11C11/5678 ,  G11C13/0004 ,  G11C17/16 ,  G11C17/165 ,  G11C2013/0078

    Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile memory device in which data stored in a memory cell is associated to whether or not the memory cell is switchable between a first state and a second state. SOLUTION: Memory cells are irreversibly programmed by applying an irreversible programming signal (I IRP ), such that the nonvolatile memory cells (21a) are made not switchable between the first state and the second state. Reading memory cells includes: assessing whether the memory cell (21a, 21b) is switchable between the first state and the second state; determining that the first irreversible logic state "1" is associated to the memory cell 21a, if the memory cell is not switchable between the first state and the second state; and determining that the second irreversible logic value "0" is associated to the memory cell (21b), if the memory cell (21b) is switchable between the first state and the second state. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种其中存储在存储单元中的数据与存储单元是否可在第一状态和第二状态之间切换的非易失性存储器件。 解决方案：通过施加不可逆编程信号（I SB> IRP ）使存储单元不可逆地编程，使得非易失性存储单元（21a）不能在第一状态和第二状态之间切换。 读存储单元包括：评估存储单元（21a，21b）是否可在第一状态和第二状态之间切换; 如果存储单元在第一状态和第二状态之间不能切换，则确定第一不可逆逻辑状态“1”与存储器单元21a相关联; 并且如果所述存储单元（21b）可在所述第一状态和所述第二状态之间切换，则确定所述第二不可​​逆逻辑值“0”与所述存储单元（21b）相关联。 版权所有（C）2009，JPO＆INPIT

    Using bit specific reference level to read memory
    7.
    发明专利
    Using bit specific reference level to read memory 有权
    使用位特定参考电平读取存储器

    公开(公告)号：JP2006286180A

    公开(公告)日：2006-10-19

    申请号：JP2006090752

    申请日：2006-03-29

    Applicant: Ovonyx Inc ,  オヴォニクス,インコーポレイテッド

    Inventor： LOWREY TYLER ,  PARKINSON WARD D ,  BEDESCHI FERDINANDO ,  RESTA CLAUDIO ,  GASTALDI ROBERTO ,  CASAGRANDE GIULIO

    IPC: G11C13/00

    CPC classification number: G11C7/14 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    Abstract: PROBLEM TO BE SOLVED: To provide a method or the like capable of creating a reading window or a reading margin more independent of the variations between bits over an arbitrary array, group or block of memory cells. SOLUTION: A voltage derived from accessing a selected bit using one read current may be utilized to read a selected bit of an untriggered phase change memory after the read current is changed. As a result, different reference voltages may be used to sense the state of more resistive versus a less resistive selected cells. The resulting read window or margin may be improved in some embodiments. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种能够创建读取窗口或读取余量的方法，该方法更加独立于存储器单元的任意阵列，组或块之间的位之间的变化。 解决方案：在读取电流改变之后，可以利用使用一个读取电流访问所选位的电压来读取未触发的相变存储器的选定位。 因此，可以使用不同的参考电压来感测比较阻性的选择的单元更多的电阻的状态。 在一些实施例中，可以改善所得到的读取窗口或边缘。 版权所有（C）2007，JPO＆INPIT

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