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    SINGLE POWER VOLTAGE TYPE NON-VOLATILE STORAGE DEVICE HAVING HIERARCHICAL COLUMN DECODER
    1.
    发明专利
    SINGLE POWER VOLTAGE TYPE NON-VOLATILE STORAGE DEVICE HAVING HIERARCHICAL COLUMN DECODER 失效

    公开(公告)号：JP2001057097A

    公开(公告)日：2001-02-27

    申请号：JP2000227650

    申请日：2000-07-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  KHOURI OSAMA ,  SACCO ANDREA ,  PICCA MASSIMILIANO

    IPC: G11C16/06 ,  G11C5/14 ,  G11C8/10

    Abstract: PROBLEM TO BE SOLVED: To obtain a single power voltage type non-volatile storage device having a hierarchical column decoder in which the bias time of a word line at the level of staircase voltage can be shortened. SOLUTION: This storage device 10 has a memory cell array 2 having structure of a form provided with global word lines 4 and local word lines 6, a global column decoding means 8 for addressing the global word lines 4, a local column decoding means 12 for addressing the local word lines 6, a global power supply means 22 for supplying power to the global column decoding means 8, and a local power supply means 24 for supplying power to a local column decoding means 12.

    CHARGE PUMP CIRCUIT AND VOLTAGE SIGNAL GENERATING METHOD
    2.
    发明专利
    CHARGE PUMP CIRCUIT AND VOLTAGE SIGNAL GENERATING METHOD 审中-公开

    公开(公告)号：JP2003153525A

    公开(公告)日：2003-05-23

    申请号：JP2002302131

    申请日：2002-10-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  PIERIN ANDREA ,  SOLTESZ DARIO ,  TORRELLI GUIDO

    IPC: G11C5/14 ,  H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To reduce the power consumption both in an operation mode state and in a stand-by mode state. SOLUTION: A charge pump circuit, connected between a reference voltage line and an output terminal, has at least two circuit stages having respective charge pump circuit elements. The circuit stages are connected between the reference voltage line and the output terminal, respectively. Further, the charge pump circuit has a control circuit, connected between the output terminal and the control terminals of the respective two circuit stages. The charge pump circuit selects a proper combination of the circuit stages, according to the current absorbed by a load connected to the output terminal.

    METHOD FOR PROGRAMMING MEMORY CELL
    3.
    发明专利
    METHOD FOR PROGRAMMING MEMORY CELL 审中-公开

    公开(公告)号：JP2002319293A

    公开(公告)日：2002-10-31

    申请号：JP2002107937

    申请日：2002-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C11/56 ,  G11C16/12

    Abstract: PROBLEM TO BE SOLVED: To realize a method for speedily and highly precisely programming a memory cell. SOLUTION: In the method for programming a non-volatile memory cell 1, at least first and second programming pulse trains F1, F2 having pulse width increasing in stages are applied continuously to a control terminal 2 of the memory cell 1, but amplitude increment between a pulse in the first programming train F1 and the next one is made larger than the amplitude increment between a pulse in the second programming train F2 and the next one. Advantageously, third programming pulse trains F0, F3, having pulse width which increases in stages, are applied to the control terminal 2 of the memory cell 1 before the first programming pulse train F1, but amplitude increment between a pulse and the next one is made smaller than the amplitude increment in the first programming train F1, and is substantially equal to the amplitude increment in the second programming train F2 or larger than the amplitude increment in the first programming train F1.

    VOLTAGE ADJUSTING CIRCUIT
    4.
    发明专利
    VOLTAGE ADJUSTING CIRCUIT 失效

    公开(公告)号：JP2001042955A

    公开(公告)日：2001-02-16

    申请号：JP2000199353

    申请日：2000-06-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  MOTTA ILARIA ,  TORELLI GUIDO

    IPC: G05F1/56 ,  G05F3/24

    Abstract: PROBLEM TO BE SOLVED: To obtain a stable voltage adjusting circuit simple in configuration. SOLUTION: This circuit is equipped with voltage dividers R1 and R2 which are connected between 1st and 2nd output terminals VDD of a source voltage generator and GND, have input terminals IN and output terminals OUT, and are connected between an output node connected to the output terminals OUT and 2nd terminals GND and an operational amplifier OP which has an inverted input terminal connected to the input terminals, an uninverted input terminal connected to an intermediate node of the voltage dividers, and an output terminal for driving a 1st field effect transistor MPU between the output node and 1st terminals; and the output terminal of the operational amplifier is connected to the output node through a compensating network COMP, and a 2nd field effect transistor MPD which is connected between the output node and the 2nd terminals and has a control terminal is provided and has its gate terminal connected to a constant-voltage generating circuit.

    6.
    发明专利
    未知

    公开(公告)号：DE60134477D1

    公开(公告)日：2008-07-31

    申请号：DE60134477

    申请日：2001-11-09

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  SOLTESZ DARIO ,  PIERIN ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  H02M3/07

    Abstract: A charge pump circuit, connected between a first voltage reference and an output terminal, comprises at least two stages consisting of an elementary charge pump circuit connected between said first voltage reference and said output terminal, and adjustment circuitry connected between said output terminal and respective control terminals of said at least two stages. This circuitry is arranged to select for actuation an appropriate combination of these elementary stages according to the current absorbed from a load connected to the output terminal.

    7.
    发明专利
    未知

    公开(公告)号：DE60323202D1

    公开(公告)日：2008-10-09

    申请号：DE60323202

    申请日：2003-02-21

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： KHOURI OSAMA ,  RESTA CLAUDIO

    IPC: G11C11/34 ,  G11C13/00 ,  G11C11/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/28 ,  G11C16/30

    Abstract: A phase change memory (20) has an array (1) formed by a plurality of cells (2), each including a memory element (3) of calcogenic material and a selection element (4) connected in series to the memory element; a plurality of address lines (11) connected to the cells; a write stage (24) and a reading stage (25) connected to the array. The write stage (24) is formed by current generators (45), which supply preset currents to the selected cells (2) so as to modify the resistance of the memory element (3). Reading takes place in voltage, by appropriately biasing the selected cell and comparing the current flowing therein with a reference value.

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