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    METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN, IN PARTICULAR FOR THE QUALITY CONTROL BY MEANS OF THE SEMICONDUCTOR DEVICE TESTING
    1.
    发明申请
    METHOD FOR AN IMPROVED CHECKING OF REPEATABILITY AND REPRODUCIBILITY OF A MEASURING CHAIN, IN PARTICULAR FOR THE QUALITY CONTROL BY MEANS OF THE SEMICONDUCTOR DEVICE TESTING 审中-公开
    用于改进测量链可重复性和可重复性的方法，特别是通过半导体器件测试的质量控制

    公开(公告)号：WO2010046724A1

    公开(公告)日：2010-04-29

    申请号：PCT/IB2008/003660

    申请日：2008-10-22

    Applicant: STMICROELECTRONICS (GRENOBLE) SAS ,  STMICROELECTRONICS S.R.L. ,  TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

    Inventor： TENUCCI, Sergio ,  PAGANI, Alberto ,  SPINETTA, Marco ,  RANCHOUX, Bernard

    IPC: G05B19/418 ,  G01R31/28

    CPC classification number: G05B19/41875 ,  G01R31/2894 ,  Y02P90/22 ,  Y02P90/86

    Abstract: The invention relates to a method for an improved checking of repeatability and reproducibility of a measuring chain, in particular for the quality control by means of the semiconductor device testing, wherein testing steps are provided for multiple and different devices to be subjected to measurement through a measuring system comprising at least one concatenation of measuring units between a testing apparatus (ATE) and each device to be subjected to measurement. Advantageously, the method comprises the following steps: checking repeatability and reproducibility of each type of unit that forms part of the measuring chain of the concatenation; then making a correlation between the various measuring chains as a whole to check repeatability and reproducibility, using a corresponding device subjected to measurement.

    Abstract translation: 本发明涉及一种用于改进测量链的重复性和再现性检查的方法，特别是通过半导体器件测试进行质量控制的方法，其中为多个和不同的器件提供测试步骤以通过 测量系统包括测试装置（ATE）和待测量的每个装置之间的测量单元的至少一个级联。 有利地，该方法包括以下步骤：检查构成级联测量链的一部分的每种类型的单元的重复性和重复性; 然后在各测量链之间进行整体的相关性，以检查重复性和再现性，使用相应的测量装置。

    SECURITY SYSTEM FOR AT LEAST AN IC INTEGRATED CIRCUIT, SECURELY INTEGRATED CIRCUIT CARD AND METHOD OF SECURE WIRELESS COMMUNICATION
    5.
    发明申请
    SECURITY SYSTEM FOR AT LEAST AN IC INTEGRATED CIRCUIT, SECURELY INTEGRATED CIRCUIT CARD AND METHOD OF SECURE WIRELESS COMMUNICATION 审中-公开
    用于至少一个IC集成电路的安全系统，安全集成电路卡和安全无线通信的方法

    公开(公告)号：WO2012019768A1

    公开(公告)日：2012-02-16

    申请号：PCT/EP2011/004030

    申请日：2011-08-11

    Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto ,  GIRLANDO, Giovanni

    Inventor： PAGANI, Alberto ,  GIRLANDO, Giovanni

    IPC: G06K19/073

    CPC classification number: G06K7/00 ,  G06K7/10178 ,  G06K19/025 ,  G06K19/072 ,  G06K19/07327 ,  G06K19/07336 ,  G06K19/07735 ,  G06K19/07756 ,  G06K19/07771 ,  G06K19/07775 ,  G06K19/07779

    Abstract: The invention relates to a security system comprising at least one integrated circuit (24a) and a transceiver / transponder circuit (30), the at least one integrated circuit (24a) being provided with an antenna (36) for communicating with the transceiver / transponder circuit (30), an inhibiting element (24b, 44, 44a, 44b) being associated with the at least one integrated circuit (24a) for inhibiting communications with the transceiver / transponder circuit (30) and for securing the data contained in the at least one integrated circuit (24a). Advantageously, the inhibiting element (24b, 44, 44a, 44b) is an electromagnetic inhibiting element, the security system further comprising a coupling element (22) that is associated with the antenna (36) of the at least one integrated circuit (24a) for temporarily deactivating the electromagnetic inhibiting element (24b, 44, 44a, 44b) to allow communications between the at least one integrated circuit (24a) and the transceiver / transponder circuit (30).

    Abstract translation: 本发明涉及一种包括至少一个集成电路（24a）和收发器/应答器电路（30）的安全系统，所述至少一个集成电路（24a）设置有天线（36），用于与收发器/应答器 电路（30），与所述至少一个集成电路（24a）相关联的禁止元件（24b，44,44a，44b），用于禁止与所述收发器/应答器电路（30）的通信并且用于保护包含在所述收发器/ 至少一个集成电路（24a）。 有利地，禁止元件（24b,44,44a，44b）是电磁抑制元件，所述安全系统还包括与所述至少一个集成电路（24a）的天线（36）相关联的耦合元件（22） 用于临时停用所述电磁抑制元件（24b,44,44a，44b）以允许所述至少一个集成电路（24a）与所述收发器/应答器电路（30）之间的通信。

    CIRCUIT FOR THE PARALLEL SUPPLYING OF POWER DURING TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER
    6.
    发明申请
    CIRCUIT FOR THE PARALLEL SUPPLYING OF POWER DURING TESTING OF A PLURALITY OF ELECTRONIC DEVICES INTEGRATED ON A SEMICONDUCTOR WAFER 审中-公开
    在半导体器件集成的大量电子器件测试期间并行供电的电路

    公开(公告)号：WO2010015388A1

    公开(公告)日：2010-02-11

    申请号：PCT/EP2009/005655

    申请日：2009-08-05

    Applicant: STMICROELECTRONICS S.R.L. ,  PAGANI, Alberto

    Inventor： PAGANI, Alberto

    IPC: H01L23/58 ,  G01R31/28

    CPC classification number: H01L22/32 ,  G01R31/2884 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to a circuit architecture for the parallel supplying of power during an electric or electromagnetic testing, such as EMWS or EWS or WLBI testing, of a plurality of electronic devices (2) each integrated on a same semiconductor wafer (1) wherein the electronic devices (1) are neatly provided on the semiconductor wafer (1) through integration techniques and have edges (5) bounded by separation scribe lines (7). Advantageously according to the invention, the circuit architecture comprises: - at least one conductive grid (4), interconnecting at least one group of the electronic devices (2) and having a portion being external (14) to the devices of the group and a portion being internal (13) to the devices of the group; the external portion (14) of the conductive grid (4) being extended also along the separation scribe lines (7); the internal portion (13) being extended within at least a part of the devices of the group; interconnection pads (6) between the external portion (14) and the internal portion (13) of the conductive grid (4) being provided on at least a part of the devices of the group, the interconnection pads (6) forming, along with the internal and external portions, power supply lines which are common to different electronic devices (2) of the group.

    Abstract translation: 本发明涉及用于在电子或电磁测试（例如EMWS或EWS或WLBI测试）中并行供电的电路架构，每个电子设备（2）均集成在相同的半导体晶片（1）上，其中 电子器件（1）通过积分技术整齐地设置在半导体晶片（1）上并且具有由分隔划线（7）限定的边缘（5）。 有利地，根据本发明，电路架构包括： - 至少一个导电栅格（4），其将至少一组电子设备（2）互连并且具有到该组的设备的外部（14）的部分，以及 部分是内部（13）到组的装置; 导电栅格（4）的外部部分（14）也沿着分隔划线（7）延伸; 所述内部部分（13）在所述组的装置的至少一部分内延伸; 在外部部分（14）和导电栅格（4）的内部部分（13）之间的互连焊盘（6）设置在该组的至少一部分器件上，互连焊盘（6）连同 内部和外部部分，该组的不同电子设备（2）共同的电源线。

    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF
    7.
    发明申请
    INTEGRATED OPTOELECTRONIC DEVICE WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF 审中-公开

    公开(公告)号：WO2014006570A8

    公开(公告)日：2014-01-09

    申请号：PCT/IB2013/055430

    申请日：2013-07-02

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： PAGANI, Alberto ,  MOTTA, Alessandro ,  LOI, Sara

    IPC: G02B6/12 ,  G02B6/43

    Abstract: An integrated electronic device, delimited by a first surface (S 1 ) and by a second surface (S 2 ) and including: a body (2) made of semiconductor material, formed inside which is at least one optoelectronic component chosen between a detector (30) and an emitter (130); and an optical path (OP), which is at least in part of a guided type and extends between the first surface and the second surface, the optical path traversing the body. The optoelectronic component is optically coupled, through the optical path, to a first portion of free space and a second portion of free space, which are arranged, respectively, above and underneath the first and second surfaces.

    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS
    8.
    发明申请
    PACKAGED ELECTRONIC DEVICE COMPRISING INTEGRATED ELECTRONIC CIRCUITS HAVING TRANSCEIVING ANTENNAS 审中-公开
    包含收发天线的集成电子电路的包装电子设备

    公开(公告)号：WO2013128348A2

    公开(公告)日：2013-09-06

    申请号：PCT/IB2013/051422

    申请日：2013-02-21

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： PAGANI, Alberto

    CPC classification number: H01Q1/2283 ,  H01L21/56 ,  H01L23/13 ,  H01L23/48 ,  H01L23/481 ,  H01L23/66 ,  H01L24/24 ,  H01L25/03 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/73259 ,  H01L2225/06524 ,  H01L2225/06531 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/1011 ,  H01L2225/1047 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A base (2) carries a first chip (3) and a second chip (4) oriented differently with respect to the base and packaged in a package (6). Each chip integrates an antenna and a magnetic via (13). A magnetic coupling path connects the chips, forming a magnetic circuit that enables transfer of signals and power between the chips (3, 4) even if the magnetic path is interrupted, and is formed by a first stretch (5c) coupled between the first magnetic-coupling element (13) of the first chip and the first magnetic-coupling element (12) of the second chip, and a second stretch (5f) coupled between the second magnetic-coupling element (12) of the first chip and the second magnetic-coupling element (13) of the second chip. The first stretch has a parallel portion (5c1, 5c3) extending parallel to the faces (2a, 2b) of the base. The first and second stretches have respective transverse portions (5i1, 5i2) extending on the main surfaces of the second chip, transverse to the parallel portion.

    Abstract translation: 基座（2）承载相对于基座不同定向并封装在封装（6）中的第一芯片（3）和第二芯片（4）。 每个芯片集成天线和磁通（13）。 磁耦合路径连接芯片，形成磁路，即使磁路被中断也能够在芯片（3,4）之间传递信号和电力，并且通过耦合在第一磁性体之间的第一拉伸（5c）形成 第一芯片的耦合元件（13）和第二芯片的第一磁耦合元件（12）以及耦合在第一芯片的第二磁耦合元件（12）和第二芯片之间的第二拉伸（5f） 第二芯片的磁耦合元件（13）。 第一拉伸具有平行于基部的表面（2a，2b）延伸的平行部分（5c1,5c3）。 第一和第二延伸部具有横向于平行部分的在第二芯片的主表面上延伸的相应横向部分（5i1,5i2）。

    INTEGRATED ELECTRONIC DEVICE FOR MONITORING HUMIDITY AND/OR ENVIRONMENTAL ACIDITY/BASICITY AND/OR CORROSION
    9.
    发明申请
    INTEGRATED ELECTRONIC DEVICE FOR MONITORING HUMIDITY AND/OR ENVIRONMENTAL ACIDITY/BASICITY AND/OR CORROSION 审中-公开
    用于监测湿度和/或环境酸度/基本和/或腐蚀的集成电子设备

    公开(公告)号：WO2014155348A1

    公开(公告)日：2014-10-02

    申请号：PCT/IB2014/060249

    申请日：2014-03-28

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： PAGANI, Alberto ,  MURARI, Bruno

    IPC: G01N27/22

    CPC classification number: G01N27/223 ,  G01N17/04

    Abstract: An integrated electronic device 1 for detecting at least one parameter related to humidity and/or presence of water and/or acidity/basicity of an environment surrounding the device is described. Such device 1 comprises a separation layer 14 from the surrounding environment, comprising at least one portion of insulating material 14, and further comprises a first conductive member 11 and a second conductive member 12, made of an electrically conductive material, arranged inside the separation layer 14, with respect to the surrounding environment, and separated from the surrounding environment by the separation layer 14. The device 1 also comprises a measurement module 15, having two measurement terminals 151, 152, electrically connected with the first 11 and the second 12 conductive members, respectively; the measurement module 15 is configured to provide an electric potential difference between the first 11 and the second 12 conductive members. The device 1 further comprises electrode means 13, configured to act as an electrode, arranged outside of the separation layer 14, with respect to the first 11 and the second 12 conductive members; the electrode means 13 are arranged so as to form, with the first 11 and the second 12 conductive members, an electromagnetic circuit having an electromagnetic circuit overall impedance variable based upon the exposure to environmental conditions with a variable level of humidity and/or acidity/basicity. The measurement module 15 is configured to measure the electromagnetic circuit overall impedance, which is present between the measurement terminals 151, 152, and to determine the at least one parameter to be detected, based on the overall impedance measured.

    Abstract translation: 描述了用于检测与湿度和/或水的存在和/或设备周围环境的酸度/碱度相关的至少一个参数的集成电子设备1。 这种装置1包括与周围环境的分离层14，其包括绝缘材料14的至少一部分，并且还包括布置在分离层内部的由导电材料制成的第一导电构件11和第二导电构件12 14，相对于周围环境，并且通过分离层14与周围环境分离。装置1还包括测量模块15，其具有两个测量端子151,152，与第一11和第二导电12电连接 成员分别; 测量模块15被配置为提供第一11和第二导电构件12之间的电位差。 装置1还包括电极装置13，其被配置为相对于第一11和第二导电构件作为布置在分离层14外侧的电极; 电极装置13被布置成与第一11和第二12导电构件形成电磁电路，该电磁电路具有基于暴露于具有可变湿度和/或酸度/湿度的环境条件的总体阻抗变化， 碱性。 测量模块15被配置为基于测量的总阻抗来测量存在于测量端子151,152之间的电磁回路总阻抗，并且确定要检测的至少一个参数。

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