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    Architecture for controlling dissipated power in a system on a chip and related system
    1.
    发明公开
    Architecture for controlling dissipated power in a system on a chip and related system 审中-公开
    Einchip-Systemarchitektur zur Verlustleistungskontrolle und verwandtes System

    公开(公告)号：EP1363179A1

    公开(公告)日：2003-11-19

    申请号：EP02011094.6

    申请日：2002-05-17

    Applicant: STMicroelectronics S.A. ,  STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Mantellassi, Luigi

    IPC: G06F1/32 ,  H01L23/34

    CPC classification number: G06F9/30101 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  H01L23/34 ,  H01L2924/0002 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/171 ,  H01L2924/00

    Abstract: A system-on-chip (SoC) architecture includes a plurality of blocks (12; M1, M2, ..., Mn; S1, S2, ..., Sk), each including a power control module (20) to selectively control the power dissipated by the block: For each block of said plurality (12; M1, M2, ..., Mn; S1, S2, ..., Sk) a power register (PCR) is provided to receive power control instructions to selectively control the respective power control module (20). The system also includes a power control unit (16) for writing respective power control instructions into the power control registers (PCR) of the blocks, whereby the power dissipated is controlled individually and indipendently for each block under the centralized control of the power control unit (16). For each block (12; M1, M2, ..., Mn; S1, S2, ..., Sk), a power status register (PSR) is also provided to receive status information concerning power control within the respective block. The power control unit (16) is arranged to a read said status instructions from such the power status registers (PSR).

    Abstract translation: 系统级芯片（SoC）架构包括多个块（12; M1，M2，...，Mn; S1，S2，...，Sk），每个块包括功率控制模块（20） 控制块消耗的功率：对于所述多个（12; M1，M2，...，Mn; S1，S2，...，Sk）的每个块，提供功率寄存器（PCR）以接收功率控制指令 以选择性地控制相应的功率控制模块（20）。 该系统还包括用于将各个功率控制指令写入块的功率控制寄存器（PCR）的功率控制单元（16），由此在功率控制单元的集中控制下对于每个块单独且独立地控制功率消耗 （16）。 对于每个块（12; M1，M2，...，Mn; S1，S2，...，Sk），还提供功率状态寄存器（PSR）以接收关于相应块内的功率控制的状态信息。 功率控制单元（16）被布置成从这样的电源状态寄存器（PSR）读取所述状态指令。

    Processing pipeline of pixel data of a color image acquired by a digital sensor
    4.
    发明公开
    Processing pipeline of pixel data of a color image acquired by a digital sensor 审中-公开
    由数字传感器所获取的彩色图像的流水线处理的像素数据

    公开(公告)号：EP1605400A1

    公开(公告)日：2005-12-14

    申请号：EP04425433.2

    申请日：2004-06-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Spampinato, Giuseppe ,  Pappalardo, Francesco ,  Fodera, Paolo Antonino ,  Virlinzi, Francesco ,  Capra, Alessandro

    IPC: G06T1/60 ,  G06T3/40

    CPC classification number: G06T3/4015 ,  G06T1/20

    Abstract: A color image pixel data processing pipeline for performing, among corrective and image enhancement steps, at least an interpolation on color data to generate triplets located at distinct pixel locations, including among a plurality of defect correction and image enhancement blocks at least a first color interpolation block, generating RGB information for each pixel of the input image pixel pattern, a second color interpolation block receiving the RGB pattern pixels from said first color interpolation block and rendering enhanced RGB pattern pixels, and a plurality of dedicated line memories and delay circuits associated to and cooperating with said interpolation and correction blocks for permitting real-time processing of pixel data, further includes input image pixel pattern data read/write buffers first and second, of identical capacity suitable to store a subset or pixel block (m*n) of the image data, for translating the scanning mode of pixel data being fed to the input line memory and delay circuits associated to al least said first color interpolation block of said pipeline, from linewise to columnwise, for each subset of data stored in said first and second buffers.
    The switching from linewise writing to columnwise reading of the data temporarily stored in input buffer means, reduces overall memory requisite without sensibly increasing computational overhead.

    A method of transmitting data streams on optical links, system and computer program product therefor
    5.
    发明公开
    A method of transmitting data streams on optical links, system and computer program product therefor 有权
    一种用于传输数据流的方法通过光链路，系统和计算机程序产品

    公开(公告)号：EP1475906A1

    公开(公告)日：2004-11-10

    申请号：EP03010238.8

    申请日：2003-05-07

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

    IPC: H04B10/155 ,  H04L25/49

    CPC classification number: H04L25/4908 ,  H04B10/524

    Abstract: A data stream (b(t)) including high ("1") and low ("0") logical states is transmitted over an optical link (16) by means of an optical source (15) adapted to be driven (14) via said the data stream to generate an optical signal for transmission over the optical link (16). The optical signal includes optical pulses generated at the occurrence of high logical ("1") states in said data stream (b(t)). The input data stream (b(t)) is coded (2000) into a coded data stream (B(t)) prior to the transmission over the optical link (16). The coding step minimises the logical high states ("1") in the coded data stream (B(t)), and the optical source (15) is driven by means of the coded data stream (B(t)) wherein the number of logical high states ("1") has been minimised.

    Abstract translation: 的数据流（B（t））的包括高（“1”）和低（“0”）的逻辑状态是反式mitted到由光学源的手段光链路（16）被驱动（15）angepasst（14） 通过所述数据流以生成用于传输在光链路（16）的光信号。 该光信号包括在高逻辑（“1”）状态的在所述数据流的发生（B（t））的生成的光脉冲。 输入数据流（B（t））的进行编码（2000）成编码数据流（B（t））的之前的传输在光链路（16）。 所述编码步骤最小化编码的数据流（B（t））的，和光源（15）中的逻辑高状态（“1”）由所述编码数据流的手段（B（t））的驱动worin数 逻辑高状态（“1”）已经被最小化。

    Floating-point multiplication
    6.
    发明公开
    Floating-point multiplication 审中-公开
    Gleitkommamultiplizierung

    公开(公告)号：EP1429239A2

    公开(公告)日：2004-06-16

    申请号：EP03027629.9

    申请日：2003-12-02

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Visalli, Giuseppe

    IPC: G06F7/52 ,  G06F7/48

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/49936 ,  G06F7/49947

    Abstract: In a method for multiplication of floating-point real numbers (f, FN), encoded in a binary way in sign (SGN, SN), exponent (E, EN) and mantissa (M; MN), the multiplication of the mantissa (M; MN) envisages a step of calculation of partial products, which are constituted by a set of addenda (P) corresponding to said mantissa (MN). In order to reduce the size and power consumption of the circuits designed for calculation, there is adopted a method of binary encoding which envisages setting the first bit of the mantissa (MN) to a value 1, in order to obtain a mantissa (MN) having a value comprised between 0.5 and 1.
    Also proposed are methods for rounding of the product and circuits for the implementation of the multiplication method. Also illustrated are circuits for conversion from and to encoding of floating-point real numbers according to the IEEE754 standard.
    Preferential application is in portable and/or wireless electronic devices, such as mobile telephones and PDAs, with low power-consumption requirements.

    Abstract translation: 在以二进制方式编码的符号（SGN，SN），指数（E，EN）和尾数（M; MN）的浮点实数（f，FN）的乘法方法中，尾数（ M; MN）设想了由对应于所述尾数（MN）的一组附加（P）构成的部分乘积的计算步骤。 为了减小设计用于计算的电路的尺寸和功耗，采用了一种二进制编码方法，其设想将尾数（MN）的第一比特设置为值1，以获得尾数（MN） 具有包括在0.5和1之间的值。还提出了用于实现乘法的乘积和电路的舍入的方法。 还示出了根据IEEE754标准从浮点实数转换和编码的电路。 优先应用于便携式和/或无线电子设备，例如移动电话和PDA，具有低功耗要求。

    Process and device for synchronization and codegroup identification in CDMA cellular communication systens
    7.
    发明公开
    Process and device for synchronization and codegroup identification in CDMA cellular communication systens 有权
    用于CDMA蜂窝通信系统的同步和Kodengruppe的识别的方法和装置

    公开(公告)号：EP1422832A1

    公开(公告)日：2004-05-26

    申请号：EP02425619.0

    申请日：2002-10-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Pappalardo, Francesco ,  Avellone, Giuseppe ,  Salurso, Elena ,  Galluzzo, Agostino

    IPC: H04B1/707

    CPC classification number: H04B1/70735 ,  H04B1/708 ,  H04B1/7083 ,  H04B2201/70702 ,  H04B2201/70707

    Abstract: To obtain frame synchronization and identify the cell codegroup in a cellular communication system (such as a system based upon the standard 3GPP FDD), there are available the synchronization codes (SSCH) organized in chips or letters transmitted at the beginning of respective slots. Slot synchronization is obtained previously in a first step of the operation of cell search. During a second step, there are acquired, by means of correlation (10) or fast Hadamard transform, the energy values corresponding to the respective individual letters with reference to the possible starting positions of the corresponding frame within the respective slot. Operating in a serial way (24) at the end of acquisition of the aforesaid energy values of the individual letters, or else operating in parallel, the energies of the corresponding words are determined. Of these eneriges only the maximum word-energy value and the information for the corresponding starting position are stored in a memory structure (22). Said maximum value and said starting position identify, respectively, the cell codes and the frame synchronization sought. A preferential application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95, or WBCDMA.

    Abstract translation: 以获得帧同步并识别在蜂窝通信系统中的小区的代码组（搜索作为基于标准的3GPP FDD系统），存在可在芯片或字母反式组织的同步码（SSCH）在respectivement槽的开端mitted。 时隙同步在小区搜索的手术的第一步先前获得的。 在第二步骤期间，存在被获取，通过相关性（10）的装置或几乎阿达玛变换，该能量值对应于与参考respectivement时隙内的对应的帧的可能的开始位置的respectivement单个字母。 在采集单个字母的上述能量值的所述端以串行方式（24）操作时，或者在并行操作中，对应的字的能量是确定性的开采。 论文eneriges的唯一的最大字能量值和相应的起始位置的信息被存储在存储器结构（22）。 所述最大值和所述起始位置确定，分别为小区的代码以及所寻求的帧同步。 以优惠的应用是在基于标准的移动通信系统：诸如UMTS，CDMA2000，IS95，WBCDMA码或。

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