公开(公告)号：EP1387395A1

公开(公告)日：2004-02-04

申请号：EP02425505.1

申请日：2002-07-31

Applicant: STMicroelectronics S.r.l.

Inventor： Mariani, Marcello ,  Beghin, Lorena

IPC: H01L21/3213 ,  H01L21/033

CPC classification number: H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method for manufacturing circuit structures integrated in a semiconductor substrate (1) that includes regions (2), in particular isolation regions, the method comprising the steps of:

depositing a conductive layer (3) to be patterned onto said semiconductor substrate (1);
forming a first mask (4b) of a first material on said conductive layer (3);
forming a second mask (5b) made of a second material that is different from the first and provided with first openings (10,12) of a first size (A) having spacers (8,8a) formed on their sidewalls to uncover portions of said first mask (4b) having a second width (B) which is smaller than the first;
partly etching away said conductive layer (3) through said first and second masks (4b,5b) such to leave grooves (13) of said second width (B);
removing said second mask (5a) and said spacers (8); and
etching said grooves (13) through said first mask (4b) to uncover said regions (2) provided in said substrate (1) and form conductive lines (3a).

Abstract translation: 一种用于制造集成在半导体衬底（1）中的电路结构的方法，该半导体衬底包括区域（2），特别是隔离区域，该方法包括以下步骤：将待图案化的导电层（3）沉积到所述半导体衬底（1）上， ; 在所述导电层（3）上形成第一材料的第一掩模（4b）; 形成第二掩模（5b），所述第二掩模（5b）由与所述第一材料不同的第二材料制成，并且具有形成在其侧壁上的间隔物（8,8a）的第一尺寸（A）的第一开口（10,12） 所述第一掩模（4b）的第二宽度（B）小于第一宽度; 部分地通过所述第一和第二掩模（4b，5b）蚀刻所述导电层（3），以留下所述第二宽度（B）的凹槽（13）; 去除所述第二掩模（5a）和所述隔离物（8）; 以及通过所述第一掩模（4b）蚀刻所述凹槽（13）以露出设置在所述基板（1）中的所述区域（2）并形成导电线（3a）。

公开(公告)号：EP0991115A1

公开(公告)日：2000-04-05

申请号：EP98830564.5

申请日：1998-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Beghin, Lorena ,  Canali, Francesca ,  Cazzaniga, Francesco ,  Riva, Luca ,  Romeo, Carmelo

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144

Abstract: A process for etching a dielectric layer, providing for forming over the dielectric layer (1) a layer of polysilicon (4), forming over the layer of polysilicon (4) a photoresist mask layer (5), etching the layer of polysilicon (4) using the photoresist mask layer (5) as an etching mask for selectively removing the layer of polysilicon (4), removing the photoresist mask layer (5) from over the layer of polysilicon (4), etching the dielectric layer (1) using the layer of polysilicon (4) as a mask. Subsequently, the layer of polysilicon (4) is converted into a layer of a transition metal silicide (10), and the layer of transition metal silicide (10) is etched for selectively removing the latter from over the dielectric layer (1).

Abstract translation: 一种用于蚀刻电介质层的方法，用于在介电层（1）上形成多晶硅层（4），在多晶硅层（4）上形成光致抗蚀剂掩模层（5），蚀刻多晶硅层（4） ）使用光致抗蚀剂掩模层（5）作为用于选择性地去除多晶硅层（4）的蚀刻掩模，从多晶硅层（4）上去除光致抗蚀剂掩模层（5），使用 多晶硅层（4）作为掩模。 随后，将多晶硅层（4）转换成过渡金属硅化物（10）的层，并且蚀刻过渡金属硅化物层（10），以从介质层（1）上方选择性地将其去除。