公开(公告)号：EP1582922A1

公开(公告)日：2005-10-05

申请号：EP04425243.5

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Romeo, Carmelo

IPC: G03F1/16

CPC classification number: G03F7/0015 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788

Abstract: A method of successfully defining (nanometric) geometries for plasma and/or ion implantation treatments of a semiconductor wafer has been found that is decisively more cost effective than the previously known approaches.
A reusable laminar mask of a material that is mechanically selfsustaining, lithographically definable and dry etchable is fabricated by lithographically defining on a mechanically selfsustaining laminar substrate of a dry etchable material the desired geometries and subsequently dry etching it to produce the desired apertures through the whole thickness of the substrate. After removing the resist mask used for lithographically defining and etching the apertures through the laminar substrate, a layer of a refractory material having a substantial resistance to plasmas is deposited over the surface of the defined and etched laminar substrate that will eventually face toward the plasma or the ion source.
The so fabricated mask (or mask electrode) is placed in contact or at a relatively small distance that may be comprised between 1 and 5 millimeters, from the surface of an ordinarily supported wafer to be processed and if the mask is held spaced from the surface of the wafer it is preferably coupled to an RF power source.
Most preferably, the laminar substrate should be electrically conductive because, according to preferred embodiments of this invention, the reusable mask is fed with RF power during use.
It has been found that it is possible to achieve an outstandingly higher productivity and a decisive cost abatement by avoiding the need of lithographically defining the required geometries on the semiconductor wafer as well as of defining the geometries by direct writing on a resist layer with a focused electron beam (electron brush).

公开(公告)号：EP0991115A1

公开(公告)日：2000-04-05

申请号：EP98830564.5

申请日：1998-09-28

Applicant: STMicroelectronics S.r.l.

Inventor： Beghin, Lorena ,  Canali, Francesca ,  Cazzaniga, Francesco ,  Riva, Luca ,  Romeo, Carmelo

IPC: H01L21/311 ,  H01L21/768

CPC classification number: H01L21/76802 ,  H01L21/31144

Abstract: A process for etching a dielectric layer, providing for forming over the dielectric layer (1) a layer of polysilicon (4), forming over the layer of polysilicon (4) a photoresist mask layer (5), etching the layer of polysilicon (4) using the photoresist mask layer (5) as an etching mask for selectively removing the layer of polysilicon (4), removing the photoresist mask layer (5) from over the layer of polysilicon (4), etching the dielectric layer (1) using the layer of polysilicon (4) as a mask. Subsequently, the layer of polysilicon (4) is converted into a layer of a transition metal silicide (10), and the layer of transition metal silicide (10) is etched for selectively removing the latter from over the dielectric layer (1).

Abstract translation: 一种用于蚀刻电介质层的方法，用于在介电层（1）上形成多晶硅层（4），在多晶硅层（4）上形成光致抗蚀剂掩模层（5），蚀刻多晶硅层（4） ）使用光致抗蚀剂掩模层（5）作为用于选择性地去除多晶硅层（4）的蚀刻掩模，从多晶硅层（4）上去除光致抗蚀剂掩模层（5），使用 多晶硅层（4）作为掩模。 随后，将多晶硅层（4）转换成过渡金属硅化物（10）的层，并且蚀刻过渡金属硅化物层（10），以从介质层（1）上方选择性地将其去除。

公开(公告)号：EP1582922B1

公开(公告)日：2008-11-26

申请号：EP04425243.5

申请日：2004-04-01

Applicant: STMicroelectronics S.r.l.

Inventor： Alba, Simone ,  Romeo, Carmelo

IPC: G03F1/16

CPC classification number: G03F7/0015 ,  G03F1/20 ,  H01J2237/0453 ,  H01J2237/31788

公开(公告)号：EP1043626A1

公开(公告)日：2000-10-11

申请号：EP99830195.6

申请日：1999-04-06

Applicant: STMicroelectronics S.r.l.

Inventor： Romeo, Carmelo ,  Canestrari, Paolo ,  Ruffoni, Roberto

IPC: G03F1/14 ,  G03F7/20

CPC classification number: G03F7/70433 ,  G03F1/36 ,  G03F7/70891

Abstract: In a photolithographic process using a photolithographic mask having opaque mask areas and transparent mask areas, the opaque mask areas corresponding to a pattern to be transferred onto a semiconductor wafer to form on the wafer a pattern of active structures, a method for improving the performance of the photolithographic equipment and for increasing the lifetime of the optics thereof characterized by providing auxiliary opaque mask areas (2;3;4) in areas of the mask not covered by active opaque mask areas (1), so as to reduce a transmission factor of the mask.

Abstract translation: 在使用具有不透明掩模区域和透明的掩膜区域光刻掩模的光刻工艺，不透明掩模区域对应的图案到半导体晶片被转移到形成在晶片上的活性结构的图案，为了提高的性能的方法 光刻设备和用于其通过提供辅助不透明掩模区域为特征的提高光学器件的寿命（2; 3; 4）在所述掩模的区域不被活性不透明掩模区域（1）覆盖，以便减小的透射系数 掩模。