公开(公告)号：EP1271509A1

公开(公告)日：2003-01-02

申请号：EP01830422.0

申请日：2001-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Rossi, Augusto ,  Reggiani, Lucca

IPC: G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10296 ,  G11B20/10009 ,  G11B20/1833

Abstract: The present invention relates to a method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system, that combines a Soft Output Viterbi Algorithm SOVA (39), having the capability of detecting the reliability of a discrete, equalized signal (38), and a post processor (37), having the capability of detecting specific error events in said discrete, equalized signal (38), so as to correct said error events and to generate an output bit stream (48).

Abstract translation: 本发明涉及一种用于检测并在一个大容量存储系统的磁记录信道校正误差的方法和装置，确实结合了一个软输出维特比算法SOVA（39），其具有检测离散的可靠性的能力，均衡信号 （38），以及具有在所述离散检测特定的错误事件的能力的后处理器（37），均衡后的信号（38），以便校正所述错误事件并在输出位流（48），以产生。

公开(公告)号：EP0854482B1

公开(公告)日：2004-03-31

申请号：EP97830011.9

申请日：1997-01-16

Applicant: STMicroelectronics S.r.l.

Inventor： Sannino, Roberto ,  Brenna, Filippo

IPC: G11B20/00 ,  G11B20/14 ,  H03M5/14

CPC classification number: H03M5/145 ,  G11B20/1426 ,  G11B2020/1465

公开(公告)号：EP1300955A1

公开(公告)日：2003-04-09

申请号：EP01830623.3

申请日：2001-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Reggiani, Luca ,  Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Giovenzana, Davide ,  Rossi, Augusto

IPC: H03M13/45 ,  H03M13/41

CPC classification number: H03M13/45 ,  H03M13/41

Abstract: A system (10) for decoding digital signals subjected to block coding (B) comprising a post-processor (13) which corrects (13) the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor (13) is a finite-state machine described by a graph (G) which represents the set of error events (E), the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor (13) evolves in steps through subsequent transition matrixes (G), deleting at each step the following graph paths

paths which accumulate an invalid number of error events (N E ) or an excessive number of wrong bits (N),
paths which accumulate a total reliability higher than a given threshold (β),
paths with a invalid check on the received sequence (P), and
paths which reveal an invalid syndrome (S) after having reached a maximum number of events.

Abstract translation: 一种用于对经过块编码（B）的数字信号进行解码的系统（10）（B），包括校正（13）受错误影响的码字的后处理器（13），以最可能的序列识别它们，该序列是信道序列，并满足 综合征检查。 后处理器（13）是由图（G）描述的有限状态机，其表示错误事件集合（E），定义所述错误事件集合的结构的相应转换集合。 优选地，后处理器（13）逐步演变为随后的转换矩阵（G），在每个步骤中删除累积无效数量的错误事件（NE）或过多数量的错误位（N）的以下图形路径路径， 累积高于给定阈值（β）的总可靠性的路径，对接收到的序列（P）进行无效检查的路径，以及在达到最大事件数量后显示无效综合征（S）的路径。

公开(公告)号：EP1293978A1

公开(公告)日：2003-03-19

申请号：EP01830577.1

申请日：2001-09-10

Applicant: STMicroelectronics S.r.l.

Inventor： Brenna, Filippo

IPC: G11B20/18 ,  H03M13/00

CPC classification number: H03M13/29 ,  G11B20/1866 ,  H03M13/1515 ,  H03M13/2909 ,  H03M13/293 ,  H03M13/2948

Abstract: The signals that are to be transferred, i.e., written (161) and/or read (17), with respect to the sectors of a storage medium, such as a hard disk, are encoded by using at least two error-correction codes (12, 14). Two error-correction codes (ECCs) are used of the Reed Solomon type, namely an inner code (12) and an outer code (14). At the encoded level, the user data are organized in a matrix structure comprising a first set of data sectors (for example, sixteen data sectors) and are encoded, respectively, by means of the inner code (12) in the horizontal direction of the matrix and by means of the outer code (14) in the vertical direction of the matrix. The redundancy of the outer code (14) is organized in a second set of redundancy sectors, which comprises, for example, two redundancy sectors, written and/or read with respect to said storage medium as the sectors of said first set.

Abstract translation: 要传输的信号，即写入（161）和/或读取（17）相对于存储介质（例如硬盘）的扇区，通过使用至少两个纠错码（ 12，14）。 使用Reed Solomon类型的两个纠错码（ECC），即内码（12）和外码（14）。 在编码级别，将用户数据组织成矩阵结构，该矩阵结构包括第一组数据扇区（例如，十六个数据扇区），并且通过内部码（12）在水平方向上被编码 矩阵，并且通过外部码（14）在矩阵的垂直方向上。 外码（14）的冗余被组织在第二组冗余扇区中，其包括例如相对于作为所述第一组的扇区的所述存储介质写入和/或读取的两个冗余扇区。

公开(公告)号：EP1274079A1

公开(公告)日：2003-01-08

申请号：EP01830448.5

申请日：2001-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Dati, Angelo ,  Brenna, Filippo ,  Giovenzana, Davide

IPC: G11B20/10 ,  G11B20/18 ,  G11B5/02 ,  G11B5/09

CPC classification number: G11B20/1876 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009

Abstract: Presented is a receiver in a data read channel having an input terminal for receiving an input signal provided by a transmitter of the data read channel, and producing an output signal at an output terminal, the receiver comprising:

a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted;
an interpolated timing recovery circuit coupled to an output of the FIR filter, the timing recovery circuit having an output signal coupled to the output terminal of the receiver;
a timer circuit coupled to the output terminal and feedback connected to the timing recovery circuit; wherein the coefficients of the timing recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

Abstract translation: 提出了一种数据读取通道中的接收器，具有用于接收由数据读取通道的发送器提供的输入信号并在输出端产生输出信号的输入端，该接收机包括：有限脉冲响应（FIR）滤波器 耦合到输入端子并具有能够适配的滤波器系数; 内插定时恢复电路，耦合到FIR滤波器的输出端，定时恢复电路具有耦合到接收机的输出端的输出信号; 定时器电路，耦合到所述输出端子，反馈连接到所述定时恢复电路; 其中定时恢复电路的系数通过数据读通道的信号功率谱使用成本加权函数进行动态调整。