公开(公告)号：EP1274079A1

公开(公告)日：2003-01-08

申请号：EP01830448.5

申请日：2001-07-03

Applicant: STMicroelectronics S.r.l.

Inventor： Dati, Angelo ,  Brenna, Filippo ,  Giovenzana, Davide

IPC: G11B20/10 ,  G11B20/18 ,  G11B5/02 ,  G11B5/09

CPC classification number: G11B20/1876 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10009

Abstract: Presented is a receiver in a data read channel having an input terminal for receiving an input signal provided by a transmitter of the data read channel, and producing an output signal at an output terminal, the receiver comprising:

a finite impulse response (FIR) filter coupled to the input terminal and having filter coefficients capable of being adapted;
an interpolated timing recovery circuit coupled to an output of the FIR filter, the timing recovery circuit having an output signal coupled to the output terminal of the receiver;
a timer circuit coupled to the output terminal and feedback connected to the timing recovery circuit; wherein the coefficients of the timing recovery circuit are dynamically adapted using a cost weighted function through a signal power spectrum of the data read channel.

Abstract translation: 提出了一种数据读取通道中的接收器，具有用于接收由数据读取通道的发送器提供的输入信号并在输出端产生输出信号的输入端，该接收机包括：有限脉冲响应（FIR）滤波器 耦合到输入端子并具有能够适配的滤波器系数; 内插定时恢复电路，耦合到FIR滤波器的输出端，定时恢复电路具有耦合到接收机的输出端的输出信号; 定时器电路，耦合到所述输出端子，反馈连接到所述定时恢复电路; 其中定时恢复电路的系数通过数据读通道的信号功率谱使用成本加权函数进行动态调整。

公开(公告)号：EP1622300A1

公开(公告)日：2006-02-01

申请号：EP04425589.1

申请日：2004-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Giovenzana, Davide ,  Dati, Angelo ,  Rossi, Augusto Andrea

IPC: H04L7/02

CPC classification number: G11B20/10009 ,  G11B20/10055 ,  G11B20/10222 ,  H04L7/0029 ,  H04L7/10

Abstract: The invention relates to a method and architecture for improving the robustness of a synchronization system through a minimum latency loop, for instance in the Hard Disk Drive applications, wherein synchronous detection processing is performed for timing recovering of a correct sampling phase and frequency and by a first acquisition step of the a known preamble signal pattern, for generating a timing periodic signal, followed by a second tracking step, for recovering phase, frequency and gain sampling errors of the synchronization signal including a header followed by an unknown data content.
Advantageously, a feedback loop including a numeric preamble generator (NPG) is provided for obtaining a reduced latency in the acquisition phase; such a numeric preamble generator (NPG) stores preamble values for different phase offset.

Abstract translation: 本发明涉及一种用于通过最小等待时间循环改善的同步系统的鲁棒性，例如在硬盘驱动器应用的方法和架构，worin同步检测处理，执行用于定时恢复正确的取样相位和频率，并通过一个 在一个已知的前导码信号模式的第一获取步骤，用于产生周期性的定时信号，然后第二跟踪步骤，用于恢复相位，频率和增益包括随后对未知数据的内容的报头中的同步信号的采样误差。 有利的是，反馈环包括一个数字前导码生成器（NPG）提供了用于在采集阶段获得一个减少的等待时间; 求数字前导码发生器（NPG），用于不同相位偏移存储前同步码的值。

公开(公告)号：EP1603134A1

公开(公告)日：2005-12-07

申请号：EP04425397.9

申请日：2004-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Dati, Angelo ,  Rossi, Augusto Andrea ,  Giovenzana, Davide

IPC: G11B27/30 ,  G11B20/12

CPC classification number: G11B27/3027 ,  G11B2220/20

Abstract: A method to improve data reliability on Hard Disk Drive systems wherein user data items are distributed across a set of independent sectors and appended to a header in order to ensure adequate signal amplitude and synchronization and wherein a first timing recovering phase is achieved to recover proper signal amplitude acquiring phase and frequency lock by a preamble field and a subsequent frame synchronous detection phase acquiring a sync mark field. The method takes advantage of at least a data sector comprising a first header including a first preamble and a first sync mark field and a second header including a second preamble and a second sync mark field.

Abstract translation: 一种用于提高硬盘驱动器系统上的数据可靠性的方法，其中用户数据项分布在一组独立扇区上并附加到报头，以便确保足够的信号幅度和同步，并且其中实现第一定时恢复阶段以恢复适当的信号 幅度采集相位和前同步码字段的频率锁定以及随后的帧同步检测阶段获取同步标记字段。 该方法利用至少一个数据扇区，该数据扇区包括包括第一前同步码和第一同步标记字段的第一标题，以及包括第二前同步码和第二同步标记字段的第二标题。

公开(公告)号：EP1353333A1

公开(公告)日：2003-10-15

申请号：EP02425228.0

申请日：2002-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Dati, Angelo ,  Rossi, Augusto ,  Giovenzana, Davide

IPC: G11B20/10 ,  G11B20/18 ,  H03M7/46

CPC classification number: H03M13/41 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2005/0029 ,  H03M5/145 ,  H03M7/46 ,  H03M13/31 ,  H03M13/6312 ,  H03M13/6343

Abstract: In the MSN encoded form, the symbols of each block define a running digital sum (RSD) value, defined as RDS ([a 0 a 1 ...a N-1 ]) = - Σ 1 (-1) i a where the symbols a i belong to the set {0,1} and the sum extends for values of i from 0 to N-1.
The encoder (16) is configured to satisfy at least one of the following characteristics:

a) blocks of symbols with a given length (L) are used for encoding, wherein

RDS = RDS 0 + 4.K, where
K is an integer,
RDS is the said running digital sum,
RDS 0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and

b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks.

Abstract translation: 在MSN编码形式中，每个块的符号定义运行的数字和（RSD）值，定义为 RDS（Äa0a1... aN-1Ü）= - SIGMA 1（-1） DF>其中符号ai属于集合ä0,1ü，并且对于i从0到N-1的值进行扩展。 编码器（16）被配置为满足以下特征中的至少一个：a）具有给定长度（L）的符号块用于编码，其中RDS = RDS0 + 4.K，其中K是 RDS是所述运行数字和，对于所述长度（L）的偶数值，RDS0被定义为零，并且对于所述长度（L）的奇数值定义为零，以及b）具有给定长度的符号块（ L）用于MSN编码，并且通过选择编码块来实现编码，使得运行数字和（RDS）值的集合是具有满足所需速率值的元素的最小数量的集合，被定义为长度 的输入块和输出块的长度。

公开(公告)号：EP1300955A1

公开(公告)日：2003-04-09

申请号：EP01830623.3

申请日：2001-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Reggiani, Luca ,  Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Giovenzana, Davide ,  Rossi, Augusto

IPC: H03M13/45 ,  H03M13/41

CPC classification number: H03M13/45 ,  H03M13/41

Abstract: A system (10) for decoding digital signals subjected to block coding (B) comprising a post-processor (13) which corrects (13) the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor (13) is a finite-state machine described by a graph (G) which represents the set of error events (E), the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor (13) evolves in steps through subsequent transition matrixes (G), deleting at each step the following graph paths

paths which accumulate an invalid number of error events (N E ) or an excessive number of wrong bits (N),
paths which accumulate a total reliability higher than a given threshold (β),
paths with a invalid check on the received sequence (P), and
paths which reveal an invalid syndrome (S) after having reached a maximum number of events.

Abstract translation: 一种用于对经过块编码（B）的数字信号进行解码的系统（10）（B），包括校正（13）受错误影响的码字的后处理器（13），以最可能的序列识别它们，该序列是信道序列，并满足 综合征检查。 后处理器（13）是由图（G）描述的有限状态机，其表示错误事件集合（E），定义所述错误事件集合的结构的相应转换集合。 优选地，后处理器（13）逐步演变为随后的转换矩阵（G），在每个步骤中删除累积无效数量的错误事件（NE）或过多数量的错误位（N）的以下图形路径路径， 累积高于给定阈值（β）的总可靠性的路径，对接收到的序列（P）进行无效检查的路径，以及在达到最大事件数量后显示无效综合征（S）的路径。