公开(公告)号：EP1130773A1

公开(公告)日：2001-09-05

申请号：EP00830154.1

申请日：2000-02-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Rossi, Augusto ,  Betti, Giorgio ,  Cazzaniga, Marco

IPC: H03H17/02 ,  G11B20/10

CPC classification number: H03H17/0211 ,  G11B20/10009

Abstract: The invention relates to a time-continous FIR (Finite Impulse Response) filter whereby a Hilbert transform can be implemented. The filter comprises a cascade of delay cells connected between an input terminal of the filter and an output terminal; constant filter coefficients (cO,...,cn) and a programmable time delay (Td) of the programmable filter cells are provided.
The invention also relates to a filtering method effective to enable use of this Hilbert FIR filter structure for processing signals originated by the reading of data from magnetic storage media which employ perpendicular recording.

Abstract translation: 本发明涉及一种可实现希尔伯特变换的时间连续的FIR（有限脉冲响应）滤波器。 滤波器包括连接在滤波器的输入端和输出端之间的级联延迟单元; 提供了可编程滤波器单元的恒定滤波器系数（c0，...，cn）和可编程时间延迟（Td）。 本发明还涉及一种有效使得能够使用这种希尔伯特FIR滤波器结构来处理由采用垂直记录的磁存储介质读取数据所产生的信号的滤波方法。

公开(公告)号：EP1271509A1

公开(公告)日：2003-01-02

申请号：EP01830422.0

申请日：2001-06-22

Applicant: STMicroelectronics S.r.l.

Inventor： Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Rossi, Augusto ,  Reggiani, Lucca

IPC: G11B20/10 ,  G11B20/18

CPC classification number: G11B20/10296 ,  G11B20/10009 ,  G11B20/1833

Abstract: The present invention relates to a method and apparatus for detecting and correcting errors in a magnetic recording channel of a mass storage system, that combines a Soft Output Viterbi Algorithm SOVA (39), having the capability of detecting the reliability of a discrete, equalized signal (38), and a post processor (37), having the capability of detecting specific error events in said discrete, equalized signal (38), so as to correct said error events and to generate an output bit stream (48).

Abstract translation: 本发明涉及一种用于检测并在一个大容量存储系统的磁记录信道校正误差的方法和装置，确实结合了一个软输出维特比算法SOVA（39），其具有检测离散的可靠性的能力，均衡信号 （38），以及具有在所述离散检测特定的错误事件的能力的后处理器（37），均衡后的信号（38），以便校正所述错误事件并在输出位流（48），以产生。

公开(公告)号：EP1130773B1

公开(公告)日：2007-01-03

申请号：EP00830154.1

申请日：2000-02-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pisati, Valerio ,  Rossi, Augusto ,  Betti, Giorgio ,  Cazzaniga, Marco

IPC: H03H17/02 ,  G11B20/10

CPC classification number: H03H17/0211 ,  G11B20/10009

公开(公告)号：EP1353333A1

公开(公告)日：2003-10-15

申请号：EP02425228.0

申请日：2002-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Dati, Angelo ,  Rossi, Augusto ,  Giovenzana, Davide

IPC: G11B20/10 ,  G11B20/18 ,  H03M7/46

CPC classification number: H03M13/41 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10055 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2005/0029 ,  H03M5/145 ,  H03M7/46 ,  H03M13/31 ,  H03M13/6312 ,  H03M13/6343

Abstract: In the MSN encoded form, the symbols of each block define a running digital sum (RSD) value, defined as RDS ([a 0 a 1 ...a N-1 ]) = - Σ 1 (-1) i a where the symbols a i belong to the set {0,1} and the sum extends for values of i from 0 to N-1.
The encoder (16) is configured to satisfy at least one of the following characteristics:

a) blocks of symbols with a given length (L) are used for encoding, wherein

RDS = RDS 0 + 4.K, where
K is an integer,
RDS is the said running digital sum,
RDS 0 is defined as zero for even values of the said length (L), and one for odd values of said length (L), and

b) blocks of symbols with a given length (L) are used for MSN coding and encoding is effected by selecting encoded blocks such that the set of running digital sum (RDS) values is the set with the minimum number of elements that satisfy the required rate value, defined as the ratio between the length of the input blocks and the length of the output blocks.

Abstract translation: 在MSN编码形式中，每个块的符号定义运行的数字和（RSD）值，定义为 RDS（Äa0a1... aN-1Ü）= - SIGMA 1（-1） DF>其中符号ai属于集合ä0,1ü，并且对于i从0到N-1的值进行扩展。 编码器（16）被配置为满足以下特征中的至少一个：a）具有给定长度（L）的符号块用于编码，其中RDS = RDS0 + 4.K，其中K是 RDS是所述运行数字和，对于所述长度（L）的偶数值，RDS0被定义为零，并且对于所述长度（L）的奇数值定义为零，以及b）具有给定长度的符号块（ L）用于MSN编码，并且通过选择编码块来实现编码，使得运行数字和（RDS）值的集合是具有满足所需速率值的元素的最小数量的集合，被定义为长度 的输入块和输出块的长度。

公开(公告)号：EP1300955A1

公开(公告)日：2003-04-09

申请号：EP01830623.3

申请日：2001-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Reggiani, Luca ,  Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Giovenzana, Davide ,  Rossi, Augusto

IPC: H03M13/45 ,  H03M13/41

CPC classification number: H03M13/45 ,  H03M13/41

Abstract: A system (10) for decoding digital signals subjected to block coding (B) comprising a post-processor (13) which corrects (13) the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor (13) is a finite-state machine described by a graph (G) which represents the set of error events (E), the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor (13) evolves in steps through subsequent transition matrixes (G), deleting at each step the following graph paths

paths which accumulate an invalid number of error events (N E ) or an excessive number of wrong bits (N),
paths which accumulate a total reliability higher than a given threshold (β),
paths with a invalid check on the received sequence (P), and
paths which reveal an invalid syndrome (S) after having reached a maximum number of events.

Abstract translation: 一种用于对经过块编码（B）的数字信号进行解码的系统（10）（B），包括校正（13）受错误影响的码字的后处理器（13），以最可能的序列识别它们，该序列是信道序列，并满足 综合征检查。 后处理器（13）是由图（G）描述的有限状态机，其表示错误事件集合（E），定义所述错误事件集合的结构的相应转换集合。 优选地，后处理器（13）逐步演变为随后的转换矩阵（G），在每个步骤中删除累积无效数量的错误事件（NE）或过多数量的错误位（N）的以下图形路径路径， 累积高于给定阈值（β）的总可靠性的路径，对接收到的序列（P）进行无效检查的路径，以及在达到最大事件数量后显示无效综合征（S）的路径。