公开(公告)号：EP1300955A1

公开(公告)日：2003-04-09

申请号：EP01830623.3

申请日：2001-10-03

Applicant: STMicroelectronics S.r.l.

Inventor： Reggiani, Luca ,  Betti, Giorgio ,  Brenna, Filippo ,  Dati, Angelo ,  Giovenzana, Davide ,  Rossi, Augusto

IPC: H03M13/45 ,  H03M13/41

CPC classification number: H03M13/45 ,  H03M13/41

Abstract: A system (10) for decoding digital signals subjected to block coding (B) comprising a post-processor (13) which corrects (13) the codewords affected by error, identifying them with the most likely sequence which is a channel sequence and which satisfies a syndrome check. The post-processor (13) is a finite-state machine described by a graph (G) which represents the set of error events (E), the set of respective transitions defining the structure of said set of error events. Preferably, the post-processor (13) evolves in steps through subsequent transition matrixes (G), deleting at each step the following graph paths

paths which accumulate an invalid number of error events (N E ) or an excessive number of wrong bits (N),
paths which accumulate a total reliability higher than a given threshold (β),
paths with a invalid check on the received sequence (P), and
paths which reveal an invalid syndrome (S) after having reached a maximum number of events.

Abstract translation: 一种用于对经过块编码（B）的数字信号进行解码的系统（10）（B），包括校正（13）受错误影响的码字的后处理器（13），以最可能的序列识别它们，该序列是信道序列，并满足 综合征检查。 后处理器（13）是由图（G）描述的有限状态机，其表示错误事件集合（E），定义所述错误事件集合的结构的相应转换集合。 优选地，后处理器（13）逐步演变为随后的转换矩阵（G），在每个步骤中删除累积无效数量的错误事件（NE）或过多数量的错误位（N）的以下图形路径路径， 累积高于给定阈值（β）的总可靠性的路径，对接收到的序列（P）进行无效检查的路径，以及在达到最大事件数量后显示无效综合征（S）的路径。