公开(公告)号：EP1427011A1

公开(公告)日：2004-06-09

申请号：EP02425746.1

申请日：2002-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe Alessio Maria ,  Spinella, Rosario Corrado ,  Arena, Giuseppe ,  Lorenti, Simona

IPC: H01L21/764 ,  H01L21/306 ,  H01L21/3065 ,  B81C1/00

CPC classification number: B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764

Abstract: The present invention describes a process for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2).
Advantageously, according to the invention, the process provides to form in the substrate (2) at least one trench (4) and to obtain microchannels (10) starting from a deep cavity characterised by a small surface port obtained through anisotropic etching of the at least one trench (4).
Microchannels (10) are completely buried in the substrate (2) in a completely microcrystalline structure.

Abstract translation: 本发明描述了在包括单晶硅衬底（2）的集成结构（1）中实现埋入式微通道（10）的方法。 有利地，根据本发明，该方法提供在衬底（2）中形成至少一个沟槽（4）并且从深空腔开始获得微通道（10），其特征在于通过各向异性获得的小表面端口 蚀刻所述至少一个沟槽（4）。 微通道（10）以完全微晶结构完全掩埋在基板（2）中。

公开(公告)号：EP1427010A1

公开(公告)日：2004-06-09

申请号：EP02425742.0

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81B1/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A method for manufacturing a semiconductor substrate (7) of a first concentration type is described, which comprises at least a buried insulating cavity (10b, 10d), comprising the following steps:

form on the semiconductor substrate (7) a plurality of trenches (8, 10),
form a surface layer (7a, 9a) on the semiconductor substrate in order to close superficially the plurality of trenches (8, 10) forming in the meantime at least a buried cavity (10b) in correspondence with the surface-distal end of the trenches (8, 10).

Devices manufactured with the method according to the invention are also described.

Abstract translation: 一种用于制造（7）的第一浓度类型的，描述了一种半导体衬底的方法，其包括至少一个掩埋绝缘腔（10B，10D）包括以下步骤：形式在半导体基片（7）的沟槽的多个（ 8，10），形成在半导体衬底的表面层（图7A，图9A）以闭合表面上的沟槽（8的多元性，10）（图10b），其与所述表面对应的平均时间中形成至少一个掩埋空腔 沟槽（8，10）的远端。 因此与方法雅丁本发明制造设备进行了描述。

公开(公告)号：EP1427011B1

公开(公告)日：2008-09-10

申请号：EP02425746.1

申请日：2002-12-04

Applicant: STMicroelectronics S.r.l.

Inventor： D'Arrigo, Giuseppe Alessio Maria ,  Spinella, Rosario Corrado ,  Arena, Giuseppe ,  Lorenti, Simona

IPC: H01L21/764 ,  H01L21/306 ,  H01L21/3065 ,  B81C1/00

CPC classification number: B81C1/00507 ,  G01N27/447 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764

公开(公告)号：EP2280412A2

公开(公告)日：2011-02-02

申请号：EP10184095.7

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
- a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
- a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
- a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).

Abstract translation: 1.一种半导体衬底，包括至少一个掩埋绝缘腔（10b，10d），并且包括：具有第一类型的半导体衬底（7）并具有多个沟槽（8,10）， - 表面层（7a， 以形成所述至少一个掩埋绝缘腔（10b，10d）的所述多个沟槽（8,10）的表面封闭; - 在所述表面层（7a，9a）上具有与所述半导体衬底（7）相同的第一类型的第一半导体材料层（9），所述第一半导体材料层（9）至少包括沟槽（11），所述沟槽 与所述至少一个掩埋绝缘腔（10b，10d）连通。

公开(公告)号：EP1217652A1

公开(公告)日：2002-06-26

申请号：EP00830834.8

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Camalleri, Cateno Marco ,  Lorenti, Simona ,  Cali', Denise ,  Vasquez, Patrizia ,  Ferla, Giuseppe

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

Abstract: A method of controlling the quantity and uniformity of distribution of bonded oxygen atoms at the interface between the polysilicon and the monocrystalline silicon consists in carrying out, after having loaded the wafer inside the heated chamber of the reactorand evacuated the chamber of the LPCVD reactor under nitrogen atmosphere, a treatment of the wafer with hydrogen at a temperature generally comprised between 500 and 1200°C and at a vacuum generally comprised between 0.1 Pa and 60000 Pa, and preferably at a temperature of 850°C ± 15°C and at a vacuum of 11000 Pa ± 2000 Pa, for a time generally comprised between 0.1 and 120 minutes, and most preferably between 0.5 and 1.5 minutes, in order to remove any and all the oxygen that may have combined with the silicon on the surface of the monocrystalline silicon during the loading inside the heated chamber of the reactor even if it is done under a nitrogen flux.
After such a hydrogen treatment, another treatment is carried out substantially under the same vacuum conditions and at a temperature generally comprised between 700 and 1000°C with nitrogen protoxide (N 2 O) for a time generally comprised between 0.1 and 120 minutes, preferably between 0.5 and 1.5 minutes.
The treatment with nitrogen protoxide (N 2 O) at such a vacuum and temperature conditions causes a relatively slow oxidation of the monocrystalline silicon and allows an effective control of the amount of oxygen at the interface and a great uniformity of distribution of it on the surface. The tunnel barrier characteristics in respect to the holes of the so created oxide film at the interface between the monocrystalline silicon and the polysilicon layer show an outstanding reproducibility.

Abstract translation: 在多晶硅和单晶硅之间的界面处控制键合氧原子的分布的数量和均匀性的方法包括在将晶片装入反应器的加热室内并在氮气下抽空LPCVD反应器的腔室 气氛中，在通常为500-1200℃的温度下，通常在0.1Pa和60000Pa之间的温度下，优选在850℃±15℃的温度下，用氢处理晶片， 真空度为11000Pa +/- 2000Pa，时间通常为0.1至120分钟，最优选为0.5至1.5分钟，以除去可能与表面上的硅组合的任何和全部氧 的单晶硅在反应器的加热室内加载期间即使在氮气通量下进行。 在这样的氢处理之后，基本上在相同的真空条件下和通常在700-1000℃的温度下用氮氧化丙烷（N 2 O）进行另外的处理，时间通常在0.1至120分钟之间，优选在0.5至 1.5分钟。 在这样的真空和温度条件下用氮氧化物（N 2 O）处理导致单晶硅的相对缓慢的氧化，并且允许有效地控制界面处的氧量并且在表面上具有很大的均匀分布。 相对于在单晶硅与多晶硅层之间的界面处所形成的氧化膜的孔的隧道势垒特性显示出突出的再现性。

公开(公告)号：EP2280412A3

公开(公告)日：2011-02-16

申请号：EP10184095.7

申请日：2002-11-29

Applicant: STMicroelectronics S.r.l.

Inventor： Renna, Crocifisso Marco Antonio ,  La Magna, Luigi ,  Lorenti, Simona ,  Coffa, Salvatore

IPC: H01L21/764 ,  H01L21/3063 ,  H01L21/762 ,  H01L29/06 ,  B81C1/00 ,  H01L21/302 ,  H01L21/306

CPC classification number: B81C1/00047 ,  B81B2201/0257 ,  B81C2201/0115 ,  B81C2201/0116 ,  H01L21/302 ,  H01L21/306 ,  H01L21/76243 ,  H01L21/764 ,  H01L29/0649 ,  H04R19/005

Abstract: A semiconductor substrate comprising at least a buried insulating cavity (10b, 10d) and comprising:
- a semiconductor substrate (7) having a first type of concentration and having a plurality of trenches (8, 10),
- a surface layer (7a, 9a) on said semiconductor substrate (7) in order to close superficially said plurality of trenches (8, 10) forming said at least a buried insulating cavity (10b, 10d);
- a first semiconductor material layer (9) on said surface layer (7a, 9a) having the same first type of concentration as said semiconductor substrate (7), said first semiconductor material layer (9) comprising at least a trench (11) which is in communication with said at least a buried insulating cavity (10b, 10d).

公开(公告)号：EP1217652B1

公开(公告)日：2003-09-24

申请号：EP00830834.8

申请日：2000-12-20

Applicant: STMicroelectronics S.r.l.

Inventor： Camalleri, Cateno Marco ,  Lorenti, Simona ,  Cali', Denise ,  Vasquez, Patrizia ,  Ferla, Giuseppe

IPC: H01L21/331 ,  H01L29/73

CPC classification number: H01L29/66272 ,  H01L21/2256 ,  H01L29/7311

公开(公告)号：EP1296361A1

公开(公告)日：2003-03-26

申请号：EP01830580.5

申请日：2001-09-13

Applicant: STMicroelectronics S.r.l.

Inventor： Ward, Peter ,  Ferla, Giuseppe ,  Lorenti, Simona

IPC: H01L21/20

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/2022

Abstract: A process of forming an interface free layer of silicon on a substrate of monocrystalline silicon (105) including the steps of: providing a substrate of monocrystalline silicon (105) having a surface substantially free of oxide, depositing a layer of silicon in-situ doped (120) on the surface of the substrate in an oxygen-free environment and at a temperature below 700°C for obtaining a first monocrystalline portion (120m) of the silicon layer adjacent to the substrate and a second polycrystalline portion (120p) of the silicon layer spaced apart from the substrate, and heating the layer of silicon for growing the monocrystalline portion through part of the polycrystalline portion.

Abstract translation: 具有基本上不含氧化物沉积硅原位掺杂的层的表面上提供的单晶硅衬底（105）：在硅的界面自由层的单晶硅（105）的在基板上形成包括以下步骤的方法 在无氧环境，并在低于700℃的温度下，用于获得所述硅层的第一单晶部分（120米）毗邻的基板和一个第二多晶部分（120P）的基板的表面上（120） 硅层从衬底隔开，以及用于通过所述多晶部分的一部分生长单晶部分加热硅的层。